Non-volatile Memory Dummy Pattern Etching Stopper
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges in suppressing short-circuits between adjacent memory cells and maintaining pattern integrity due to excessive etching of inter-layer insulating films, leading to stress differences and pattern deformation.
Innovation Solution
Incorporating a dummy pattern in the layer corresponding to the memory layer below the wiring in the drawing sections, which functions as a stopper during etching to reduce the etching amount and prevent pattern destruction, while ensuring sufficient etching to avoid memory cell configuring member residuals between adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the inter-layer insulating film is sufficiently etched to suppress short-circuits between adjacent memory cells, then the reliability is improved, but the pattern may become twisted due to stress difference
Solution Approach 1:
The patent applies different etching depths to different regions: the inter-layer insulating film is deeply etched in the memory cell section to prevent short-circuits, while it is lightly etched in the drawing section to maintain pattern integrity. This local differentiation resolves the contradiction between reliability improvement and pattern preservation.
Solution Approach 2:
The patent performs preliminary etching of the inter-layer insulating film in the drawing section before forming the memory cell configuring members. This preliminary action creates a stopper structure that prevents excessive etching later, thereby maintaining pattern integrity while still allowing sufficient etching in the memory cell section for reliability.
2Reliability
If the inter-layer insulating film is deeply etched in the drawing section, then the short-circuit suppression is improved, but the aspect ratio becomes large and stress difference is emphasized
Solution Approach 1:
The patent implements local quality by varying the etching depth of the inter-layer insulating film across different sections. The drawing section maintains a smaller aspect ratio with lighter etching, while the memory cell section achieves deep etching for short-circuit suppression. This resolves the contradiction between reliability and device complexity.
3Manufacturing precision
If the inter-layer insulating film is lightly etched in the drawing section, then the pattern integrity is maintained, but the memory cell configuring member may residual between adjacent cells
Solution Approach 1:
The patent applies local quality by differentiating etching depth between sections: light etching in the drawing section preserves pattern integrity, while deep etching in the memory cell section ensures complete removal of inter-layer insulating film to prevent configuring member residuals and ensure proper cell isolation.
Solution Approach 2:
The preliminary etching in the drawing section creates a controlled stopper structure that prevents over-etching. This preliminary action allows subsequent processing to achieve deep etching in memory cell sections for isolation without compromising the pattern integrity in drawing sections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the etching amount in the drawing sections, suppresses stress differences, and prevents pattern deformation, thereby enhancing the manufacturing process and device reliability.
Implementation Method 1
a first wiring material layer, which becomes the word line, and a first memory layer including a variable resistive layer, which becomes the variable resistive element, and a diode layer, which becomes a rectifier element, are stacked on an inter-layer insulating film. The first wiring material layer and the first memory layer are then etched to a line-and-space pattern extending in the first direction through a lithography technique and a reactive ion etching technique
Data Source
AI summary
According to one embodiment, a memory cell section includes a memory layer in which a non-volatile memory cell is arranged at an intersecting position of a first wiring and a second wiring to be sandwiched by the first wiring and the second wiring. A first drawing section connects the memory cell section and a first contact section with the first wiring, and a second drawing section connects the memory cell section and a second contact section with the second wiring. A dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.