Thin Film Transistor Array Panel Pad Connection Design
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Solution Overview
Problem
In liquid crystal display manufacturing, excessive thickness of the passivation layer on thin film transistor array panels leads to increased height of contact holes, causing disconnection issues between driving circuits and pad portions, and the use of organic insulators further exacerbates this problem, while also increasing manufacturing costs due to the need for multiple photomasks in the photolithography process.
Innovation Solution
A thin film transistor array panel design that reduces the height difference between pad portions and connecting members by eliminating the thick organic insulator at the pad portions, using an assistance pad portion and a gate insulating layer to form contact holes, and employing a manufacturing method that forms connecting members with the same layer as the field generating electrodes, thereby preventing the need for additional photomasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an organic insulator is used as passivation layer, then ease of manufacture is improved, but the contact hole height is further increased exacerbating disconnection issues
Solution Approach 1:
The organic insulator passivation layer is segmented with complete removal at the pad portion and thin retention elsewhere, maintaining manufacturing ease while preventing disconnection at critical connection points.
Solution Approach 2:
The organic insulator is applied with local quality variation: full thickness in transistor regions for insulation, and complete removal at pad regions for reliable connection, resolving the contradiction between ease of manufacture and connection reliability.
2Manufacturing precision
If multiple photomasks are used for photolithography process, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
Multiple patterning functions are merged into a single photomask design that simultaneously defines transistor patterns and pad portion patterns, reducing photomask count while maintaining manufacturing precision through integrated pattern design.
Solution Approach 2:
The photomask is designed with multi-functionality to perform multiple patterning tasks in one exposure step, including transistor active area definition and pad portion pattern definition, thereby reducing manufacturing cost while maintaining precision.
Data Source
AI summary
A thin film transistor array panel includes: an substrate; a gate line and a gate pad portion disposed on the substrate; a gate insulating layer disposed on the gate line and the gate pad portion; a data line and a data pad portion disposed on the gate insulating layer; a gate assistance pad portion disposed at a position corresponding to the gate pad portion; a first insulating layer disposed on the data line and removed at the gate pad portion and the data pad portion; a first field generating electrode disposed on the first insulating layer; a second insulating layer disposed on the first field generating electrode and removed at the gate pad portion and the data pad portion; and a second field generating electrode disposed on the second insulating layer. The assistance gate pad portion and the gate insulating layer include a contact hole exposing the gate pad portion.