Backside Contact Formation in Bulk-to-SOI Semiconductor Devices
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Solution Overview
Problem
As semiconductor devices continue to scale down, forming conductive contacts to electrically connect source/drain and gate terminals becomes increasingly challenging due to limited space, and existing methods for forming backside contacts on bulk substrates face difficulties in reducing parasitic capacitance and improving source/drain contact resistance.
Innovation Solution
The method involves forming semiconductor fins on a bulk substrate, depositing insulator layers, and creating a gate stack over the channel region, followed by bonding a handle wafer and thinning the substrate to expose backside regions for contact formation, which mimics the structure of a semiconductor-on-insulator substrate to reduce capacitance and enhance contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling is pursued to reduce costs and power consumption, then productivity and power efficiency are improved, but manufacturing precision and contact formation difficulty worsen due to limited space
Solution Approach 1:
The patent transitions from planar contact formation to three-dimensional contact structures by forming contacts through the thickness of the substrate and utilizing vertical sidewalls. This dimensional change allows contacts to be formed in the depth direction rather than competing for limited lateral space, enabling continued device scaling while maintaining manufacturable contact dimensions
Solution Approach 2:
The substrate is divided into front and back sides with distinct functional regions. The contact formation process is segmented into separate stages: front-side device fabrication, substrate thinning, and back-side contact formation. This segmentation allows each process to be optimized independently, improving manufacturing precision for contacts without compromising device scaling
2Ease of manufacture
If conventional contact formation methods are used on bulk substrates, then ease of manufacture is maintained, but parasitic capacitance increases and source/drain contact resistance worsens
Solution Approach 1:
The patent inverts the conventional approach by forming contacts on the backside of the substrate rather than on the front side where devices are located. This inversion allows contacts to be formed in regions with larger available space, reducing contact resistance while maintaining manufacturing simplicity through standard deposition and etching processes
Solution Approach 2:
The contact formation process is extracted from the front-side device fabrication sequence and performed separately on the backside of the substrate. This separation allows contact holes to be formed in isolation with optimized dimensions, reducing parasitic capacitance between contacts and improving contact resistance without interfering with device manufacturing
3Area of stationary object
If substrate thickness is reduced to expose backside regions, then contact formation area is improved, but structural strength and manufacturing complexity worsen
Solution Approach 1:
The substrate is thinned to the target thickness before contact formation begins. This preliminary action creates the optimal structure for subsequent contact deposition, allowing large contact areas to be formed on the exposed backside surface without requiring complex in-situ thinning during the contact formation process itself
Solution Approach 2:
The substrate itself serves as an intermediary structure that is processed to a specific thinness to enable backside contact formation. By controlling the substrate thickness as an intermediate parameter, the patent balances the need for large contact areas with the requirements for structural integrity and manufacturing feasibility
Data Source
AI summary
A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.