Display Device Mask Reduction via Half-Tone Patterning
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Solution Overview
Problem
The existing display device fabrication processes require multiple mask steps, leading to decreased efficiency and increased costs due to the complexity of patterning wirings and insulating films.
Innovation Solution
A method and structure for reducing the number of masks used in the fabrication process by employing a half-tone mask with light blocking and transmitting parts of different transmittances to pattern conductive and semiconductor layers simultaneously, allowing for the formation of conductive patterns that electrically couple light blocking and semiconductor patterns without the need for separate mask processes for each layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used to pattern wirings and insulating films, then patterning precision is improved, but process complexity and manufacturing time increase
Solution Approach 1:
The patent combines multiple mask processes into a single mask process by forming both the lower light blocking pattern and the upper light blocking pattern in the same conductive layer simultaneously. This merging of operations reduces the total number of masks required while maintaining the precision needed for patterning both wirings and insulating films.
Solution Approach 2:
The single mask used in the invention serves multiple functions: it patterns both the lower light blocking pattern and the upper light blocking pattern, and it defines both wiring structures and insulating film regions. This multi-functionality eliminates the need for separate specialized masks for each patterning task.
2Manufacturing precision
If multiple mask processes are used to pattern wirings and insulating films, then patterning precision is improved, but manufacturing time increases
Solution Approach 1:
The patent merges sequential mask operations into a single simultaneous operation. By forming both the lower and upper light blocking patterns in one mask process, the total manufacturing time is reduced while the precision requirements for both patterns are still met through careful design of the mask geometry and light exposure parameters.
3Manufacturing precision
If separate mask processes are used for each layer, then manufacturing precision is maintained, but the number of process steps increases
Solution Approach 1:
The invention merges the patterning of multiple layers into a single process step. The conductive layer is patterned once to simultaneously create both the lower light blocking pattern (which becomes part of the wiring structure) and the upper light blocking pattern (which defines the insulating film regions), thereby maintaining precision while improving productivity.
4Productivity
If a reduced number of masks is used, then process efficiency is improved, but patterning complexity per mask increases
Solution Approach 1:
The mask design is segmented into distinct functional regions: areas that will form the lower light blocking pattern, areas that will form the upper light blocking pattern, and areas that will remain as insulating films. This segmentation allows the single mask to handle multiple patterning tasks while keeping the design manageable through clear spatial organization of different pattern regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of mask processes, enhancing process efficiency and lowering costs by allowing for the simultaneous patterning of multiple layers, thereby simplifying the fabrication of display devices.
Implementation Method 1
a half-tone mask with light blocking and transmitting parts of different transmittances to pattern conductive and semiconductor layers simultaneously
Data Source
AI summary
A display device and a method of driving a display device are provided. A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern, a buffer layer on the first conductive layer, a semiconductor layer including a semiconductor pattern on the buffer layer, a gate insulating layer on the semiconductor pattern, a second conductive layer including a gate electrode on the gate insulating layer, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including a first conductive pattern electrically coupling the lower light blocking pattern to the semiconductor pattern, wherein the first conductive pattern is coupled to the lower light blocking pattern through a first contact hole passing through the planarization layer and the buffer layer, and coupled to the semiconductor pattern through a second contact hole passing through the planarization layer.