3D Semiconductor Fabrication via Mold Structure Stacking
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost and complexity of fine pattern forming technologies, necessitating the development of three-dimensional semiconductor devices with vertically arranged memory cells to enhance integration density.
Innovation Solution
A method for fabricating three-dimensional semiconductor devices involves forming a substrate with peripheral and cell array regions, creating a peripheral structure, and sequentially depositing sacrificial and insulating layers to form a mold structure, which includes alternating upper sacrificial and insulating layers, allowing for the formation of a staircase structure that increases integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically arranged memory cells. The mold structure with alternating sacrificial and insulating layers enables vertical stacking, increasing integration density by utilizing the third dimension while maintaining manufacturing feasibility through systematic layer formation processes
2Quantity of substance
If fine pattern forming technology is advanced to increase integration, then integration density improves, but manufacturing cost and complexity increase
Solution Approach 1:
The patent divides the structure into alternating sacrificial layers and insulating layers, with each layer serving a specific function. The mold structure is segmented into multiple stacked layers that can be formed sequentially, simplifying the manufacturing process while achieving high integration density through vertical arrangement rather than complex lateral patterning
3Quantity of substance
If three-dimensional vertically arranged memory cells are formed, then integration density increases, but height difference between cell array and peripheral circuit regions increases
Solution Approach 1:
The patent applies different treatments to different regions: the mold structure with alternating layers is formed specifically on the cell array region, while the peripheral circuit region maintains its original structure. This localized approach enables vertical stacking where needed while preserving the height profile in peripheral regions, thereby reducing overall height difference
4Quantity of substance
If mold structure with alternating sacrificial and insulating layers is formed, then integration density increases, but manufacturing process complexity increases
Solution Approach 1:
The sacrificial layers and insulating layers are formed in advance as a complete mold structure before the actual memory cell formation. This preliminary structuring simplifies subsequent manufacturing steps by providing a pre-configured template that guides the formation of vertically arranged memory cells, reducing overall process complexity
Data Source
AI summary
A method of fabricating a three-dimensional semiconductor device is provided. The method includes providing a substrate with a peripheral circuit region and a cell array region; forming a peripheral structure on the peripheral circuit region, and forming an electrode structure on the cell array region. The electrode structure includes a lower electrode, a lower insulating planarized layer on the lower electrode, and upper electrodes and upper insulating layers vertically and alternatingly stacked on the lower insulating planarized layer, and the lower insulating planarized layer may be extended to cover the peripheral structure on the peripheral circuit region. An upper insulating planarized layer is formed to cover the electrode structure and the lower insulating planarized layer on the peripheral circuit region.