Semiconductor Storage Device Pad Arrangement for Chip Size Reduction
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Solution Overview
Problem
Conventional semiconductor storage devices face challenges in reducing chip size due to mechanical limitations in wire bonding, which also lead to degraded electrical characteristics from noise interference between data pads and input/output control circuits.
Innovation Solution
The arrangement of multiple data pads on both outer and inner peripheries with complementary transistors of different electroconductive types reduces the lateral width of the pad forming region, eliminates excess space, and shortens wiring lines, thereby decreasing chip size and noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If data pads are arranged only on the outer periphery of the chip, then wire bonding is mechanically feasible, but the chip size increases due to excess region and longer wiring lines
Solution Approach 1:
The patent extends the pad arrangement from a single outer periphery to include both outer and inner peripheries of the chip, utilizing the inner peripheral region to reduce the lateral width of the pad forming region and eliminate excess space, thereby reducing chip size and wiring line lengths while maintaining electrical performance
2Area of stationary object
If data pads are moved closer to input/output control circuits to reduce chip size, then chip size decreases, but electrical characteristics degrade due to noise from data pads
Solution Approach 1:
The patent combines complementary transistors (first and second transistors of different electroconductive types) into integrated transistor units positioned between the data pads and input/output control circuits. These merged transistor structures act as shielding elements that block noise from data pads from interfering with the control circuits, thereby improving electrical characteristics while enabling closer pad placement
3Area of stationary object
If lateral width of pad forming region is reduced by arranging pads on inner periphery, then chip size decreases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the pad forming region into distinct outer peripheral and inner peripheral zones, with data pads systematically arranged in parallel rows on both peripheries. This segmentation approach, combined with the regular placement of complementary transistors between pads and control circuits, creates a modular pattern that reduces manufacturing complexity despite the extended pad arrangement
Data Source
AI summary
An excess region on a chip plane is eliminated to reduce a chip size. A plurality of data pads, which input/output data, are arranged near one side of an outer periphery of a substrate in parallel with the aforementioned one side, and a plurality of data pads, which input/output data, are arranged on an inner side of the plurality of data pads in parallel with the plurality of data pads. NMOSs, which output data, are arranged between the data pads, and PMOSs, which output data, are arranged at positions where they face the NMOSs near the data pads.