Silicide Layer Stress Management in Semiconductor Memory Devices
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Solution Overview
Problem
In semiconductor device manufacturing, the silicide layer on the gate electrode of memory cells tends to disconnect due to high tensile stress, leading to a significant decrease in operation speed, while high tensile stress on the source/drain region improves transistor performance but poses a risk of disconnection.
Innovation Solution
A method involving a salicide process with high temperature heat for the source/drain region and a low temperature heat process for the gate electrode, using a nickel-platinum alloy to form silicide layers with varying platinum segregation, ensuring high tensile stress on the source/drain region and low stress on the gate electrode to prevent disconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature heat process is used to form silicide layer on source/drain region, then tensile stress is enhanced and transistor performance is improved, but silicide layer on gate electrode may disconnect
Solution Approach 1:
The patent applies different heat treatment temperatures to different regions: high temperature (600-800°C) for source/drain region silicide layers to generate tensile stress, and low temperature (400-600°C) for gate electrode silicide layers to prevent disconnection. This local differentiation resolves the contradiction between improving transistor performance and maintaining silicide layer integrity.
Solution Approach 2:
The silicide formation process is segmented into two distinct stages: first forming silicide on source/drain regions with high temperature heat treatment, then forming silicide on gate electrodes with low temperature heat treatment. This segmentation allows each region to receive optimized treatment appropriate to its functional requirements.
2Ease of operation
If high tensile stress is applied to silicide layer on source/drain region, then channel mobility is improved, but silicide layer disconnection occurs
Solution Approach 1:
The patent implements spatially differentiated heat treatment where source/drain regions receive high temperature treatment to induce tensile stress for improved channel mobility, while gate electrodes receive low temperature treatment to maintain structural continuity and prevent disconnection.
Solution Approach 2:
The patent changes the temperature parameter of heat treatment based on location: 600-800°C for source/drain regions to maximize stress-induced mobility enhancement, and 400-600°C for gate electrodes to balance stress control with connection reliability.
3Ease of manufacture
If single heat treatment process is used for both source/drain and gate electrode, then manufacturing is simplified, but cannot simultaneously optimize performance and prevent disconnection
Solution Approach 1:
The manufacturing process is segmented into sequential silicide formation steps with distinct heat treatments: first step for source/drain regions with high temperature, second step for gate electrodes with low temperature. This segmentation enables simultaneous optimization of both performance and reliability that would be impossible with a single unified process.
Solution Approach 2:
The patent performs preliminary silicide formation on source/drain regions with high temperature heat treatment before forming silicide on gate electrodes. This preliminary action allows the source/drain regions to achieve optimal stress characteristics before the gate electrode silicide is formed, preventing subsequent disconnection issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by maintaining high tensile stress on the source/drain region while preventing disconnection of the silicide layer on the gate electrode, thereby improving semiconductor device performance and reliability.
Implementation Method 1
a silicide layer is formed on a source/drain region by a salicide process with high temperature heat process, and then, a silicide layer is formed on a gate electrode of a MONOS memory by a salicide process with low temperature heat process
Implementation Method 2
an amount of platinum per unit area in a lower surface of the first silicide layer on the source/drain region of each of the MONOS memory and MISFET mixedly mounted on the substrate is larger than an amount of platinum per unit area in a lower surface of the second silicide layer on the gate electrode of the MONOS memory
Implementation Method 3
If a tensile stress of the silicide layer on the source/drain region of the MISFET can be enhanced, a property of the MISFET can be improved by inducing the tensile stress onto the channel region
Implementation Method 4
when the tensile stress of the silicide layer on the gate electrode of the memory cell is large, the silicide layer tends to be disconnected, and therefore, there is a problem of significant decrease in the operation speed of the element due to the disconnection of the silicide layer
Data Source
AI summary
A semiconductor device having a memory cell includes: a first gate electrode formed on a semiconductor substrate via a first insulating film; a second gate electrode formed on the semiconductor substrate via the second insulating film having a charge storage portion inside so as to be adjacent to the first gate electrode; a third insulating film interposed between the first gate electrode and the second gate electrode; a first source/drain region formed on a main surface of the semiconductor substrate; a first silicide layer formed in contact with an upper surface of the first source/drain region; a second silicide layer formed in contact with an upper surface of the first gate electrode; and a third silicide layer formed in contact with an upper surface of the second gate electrode. The first to third silicide layers contain platinum.