Monolithic SRAM DRAM Integration for Memory Density
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Solution Overview
Problem
There is a need for improved memory architectures in integrated circuits that enhance memory density, reduce power consumption, and increase read/write operation speed while maintaining reliability, particularly for portable electronic devices.
Innovation Solution
The integration of dynamic random access memory (DRAM) cells with memory tag circuitry, including static random access memory (SRAM) cells, in a monolithic integrated circuit die, where the DRAM cells are vertically aligned with the SRAM cells, allowing for efficient memory address validation and data retrieval, and can be further supported by additional circuitry in separate dies or substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory tag circuitry is integrated with DRAM cells in a monolithic IC die, then memory density and retrieval speed are improved, but device complexity increases
Solution Approach 1:
The patent merges memory tag circuitry (SRAM cells) with DRAM cells into a single monolithic IC die, creating an integrated memory structure where tag circuitry and data storage coexist in close proximity. This combining of previously separate components enables faster address validation and data retrieval while increasing overall memory density.
Solution Approach 2:
The patent utilizes vertical stacking arrangements where SRAM tag circuitry is positioned in one lateral plane and DRAM cells in another lateral plane, with vertical alignment between corresponding structures. This three-dimensional integration approach increases memory density without significantly expanding the lateral footprint, effectively adding a vertical dimension to the memory architecture.
2Area of stationary object
If memory tag circuitry is integrated with DRAM cells, then the memory array footprint is reduced, but manufacturing precision requirements increase
Solution Approach 1:
By transitioning from a two-dimensional lateral arrangement to a three-dimensional vertical stacking architecture, the patent reduces the lateral footprint of the memory array. The vertical alignment of SRAM tag circuitry with DRAM cells allows compact integration without requiring large lateral spacing, thereby minimizing the overall memory array footprint.
Solution Approach 2:
The patent implements a nested structure where SRAM tag circuitry is vertically aligned and positioned directly over or under DRAM cells, creating a compact integrated unit. This nesting arrangement allows the tag circuitry to occupy the same lateral footprint as the DRAM cells, maximizing space utilization and reducing the overall memory array area.
3Quantity of substance
If vertically aligned SRAM and DRAM cells are used, then memory density increases, but ease of manufacture decreases
Solution Approach 1:
The patent achieves increased memory density by utilizing vertical stacking of SRAM and DRAM cells in different lateral planes. This three-dimensional architecture allows more memory elements to be packed into the same lateral footprint, effectively increasing the quantity of memory storage without proportionally increasing the manufacturing complexity of individual cell structures.
Solution Approach 2:
The patent employs universal fabrication processes that can accommodate both SRAM and DRAM cell formation within the same monolithic IC die. By using compatible manufacturing techniques and materials for both memory types, the patent reduces the overall fabrication process complexity despite the increased density achieved through vertical integration.
Data Source
AI summary
Memory device architectures including integrated static random access memory based tag circuitry and dynamic random access memory cells are discussed related to improving density and device performance Such memory device architectures include vertically aligned dynamic random access memory cells and memory tag circuitry aligned and implemented within the same monolithic integrated circuit die or on stacked interconnected monolithic integrated circuit dies.