Polysilicon Interconnect for CMOS Image Sensor Dark Current Reduction

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Solution Overview

Problem

Conventional CMOS image sensors face issues with dark current due to etch damage during the formation of metal interconnects, which affects the crystal structure of photodiodes and increases leakage current.

Innovation Solution

The use of polysilicon interconnects that contact the photodiode via an opening in the gate dielectric layer, formed using a wet etch method that minimizes crystal damage, replaces conventional metal interconnects to reduce dark current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional metal interconnects are used to connect the photodiode, then the electrical connection is established, but etch damage occurs during the formation of metal interconnects which increases dark current and junction leakage

Engineering Contradiction:
Improvedark current reductionVSAvoidetch damage to photodiode crystal structure
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A polysilicon layer is introduced as an intermediary material between the metal interconnect and the photodiode. The polysilicon layer is formed first, then the metal interconnect is formed over the polysilicon layer. This intermediary layer prevents direct contact between the etch process and the photodiode crystal structure, thereby eliminating etch damage while maintaining electrical connection functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The polysilicon layer is formed in advance before the metal interconnect formation process. By preparing this protective layer beforehand, the photodiode is shielded from subsequent etching operations that would otherwise cause crystal structure damage and increase dark current.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If standard CMOS processing techniques are used for fabrication, then fabrication costs are reduced, but etch damage during metal interconnect formation increases junction leakage

Engineering Contradiction:
Improvefabrication cost reductionVSAvoidjunction leakage reduction
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The polysilicon layer serves as a mediator that is compatible with standard CMOS processing techniques while simultaneously protecting the photodiode from etch damage. This allows the use of conventional, cost-effective manufacturing processes without compromising device reliability or increasing junction leakage.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces dark current and junction leakage in CMOS image sensors by minimizing damage to the photodiode crystal structure during the etch process, enhancing the overall performance and reliability of the image sensing device.

Implementation Method 1

formed using a wet etch method that minimizes crystal damage

Methodology Applied
Scientific EffectWet etching:

Implementation Method 2

a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS8304821B2CMOS image sensor
Publication Date: 2012.11.06 SEMICON MFG INT (SHANGHAI) CORP
  • US8304821B2 patent drawing
  • US8304821B2 patent drawing
  • US8304821B2 patent drawing

AI summary

A complementary metal oxide semiconductor (CMOS) image sensing device includes a semiconductor substrate; a photodiode defined on the substrate; a gate dielectric layer provided over the photodiode and the substrate; a polysilicon interconnect contacting a given area of the photodiode via an opening in the gate dielectric layer; a reset transistor coupled to the photodiode; a source follower transistor coupled to the photodiode; and a select transistor coupled to the source follower transistor. The given area of the photodiode defines a node that is coupled to the reset transistor and source follower transistor.