Vertical Memory Device Protective Layer for Short Circuit Prevention
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density while maintaining reliability, particularly in the vertical transistor structure where contacts passing through substrates can lead to short circuits and reduced reliability.
Innovation Solution
A memory device design that includes a protective layer within the insulating layer below the cell region, preventing contacts from connecting to circuit elements below, and using a conductive material for the protective layer to ensure reliable voltage supply and prevent short circuits, thereby enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contacts pass through the substrate to connect to circuit elements below, then electrical connection is achieved, but short circuits occur and reliability decreases
Solution Approach 1:
The patent introduces a protective layer as an intermediary component between the contact and the circuit elements below. This protective layer selectively prevents contacts from connecting to sensitive circuit elements (such as gate electrodes) while allowing connections to non-sensitive regions, thereby eliminating short circuit risks without compromising necessary electrical connections
Solution Approach 2:
The protective layer is configured with specific local properties - it is positioned only in regions where contact protection is needed, such as below gate electrode layers, while leaving other regions open for valid connections. This localized protection approach ensures that reliability is improved only where necessary, without interfering with normal device operation
2Quantity of substance
If vertical transistor structure is used to increase integration density, then more memory elements can be integrated, but contact reliability issues arise
Solution Approach 1:
The patent addresses contact reliability issues in the vertical transistor structure by moving the protection mechanism to a different spatial dimension - placing the protective layer in the vertical dimension below the substrate, rather than trying to solve the problem in the horizontal plane. This allows integration density to increase while contact reliability is maintained through the protective layer
3Reliability
If protective layer is added to prevent short circuits, then reliability improves, but device complexity increases
Solution Approach 1:
The protective layer is formed in advance during the manufacturing process, before the final device structure is completed. This preliminary action ensures that the protective function is already in place to prevent short circuits, while the protective layer itself is designed to be integrated seamlessly with existing device layers, minimizing the increase in overall device complexity
Data Source
AI summary
A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the ceil region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.