One-Pass Multilevel Memory Programming Method

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Solution Overview

Problem

Existing multiple bit per cell memory technologies face challenges with programming speed and performance due to the need for multiple program pulses, which can cause significant disturbance to neighboring cells and increase programming time.

Innovation Solution

Implementing a one-pass, multiple-level programming method that uses a single pulse sequence with program verify steps for multiple target program levels, reducing the number of program pulses and time required, and incorporating a two-phase procedure to tighten distributions and minimize disturbance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple program pulses are used to establish multiple program levels, then multiple bits per cell can be programmed, but programming time increases significantly

Engineering Contradiction:
Improvestorage capacityVSAvoidprogramming time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing a first one-pass incremental pulse program sequence to establish preliminary program levels before performing a second one-pass sequence to establish final target program levels. This preliminary programming step allows the memory cells to be pre-positioned closer to their final states, reducing the number of additional pulses needed to achieve multiple bit storage, thereby decreasing overall programming time while maintaining high storage capacity.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If multiple program pulses are applied during programming, then multiple program levels can be established, but disturbance to non-target cells increases

Engineering Contradiction:
Improvestorage capacityVSAvoidcell disturbance
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent segments the programming operation into two distinct phases: a first one-pass incremental pulse program sequence for establishing preliminary program levels, and a second one-pass incremental pulse program sequence for establishing final target program levels. Each phase uses verify steps to monitor progress. This segmentation allows for controlled, staged programming that reduces unnecessary pulses applied to non-target cells, thereby minimizing disturbance while achieving multiple bit per cell storage capacity.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If traditional multi-pass programming is used for multiple bit per cell, then program levels can be established, but programming throughput decreases

Engineering Contradiction:
Improvestorage capacityVSAvoidprogramming throughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent merges multiple programming operations into a unified two-phase one-pass approach. Instead of executing separate multi-pass sequences for each program level, the invention combines all preliminary and final programming operations into two consolidated one-pass sequences with integrated verify steps. This merging eliminates redundant pulses and operations, significantly improving programming throughput while maintaining the ability to establish multiple program levels for high storage capacity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9685233B2Programming multibit memory cells
Publication Date: 2017.06.20 MACRONIX INTERNATIONAL CO LTD
  • US9685233B2 patent drawing
  • US9685233B2 patent drawing
  • US9685233B2 patent drawing

AI summary

A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.