Multi-Layer Mask Patterning for High-Aspect-Ratio NAND Memory Trenches

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Solution Overview

Problem

As the number of stacks in NAND semiconductor memory devices increases to enhance memory capacity, fine patterning of the stacked body becomes increasingly difficult due to the challenges in maintaining precise etching configurations and preventing deformation of mask layers, leading to issues in achieving the desired etched structure.

Innovation Solution

The method involves forming a first mask layer with a shielding portion and opening, followed by a second mask layer with intersecting openings, allowing for selective removal of layers at the crossing points to maintain etching resistance and prevent deformation, thereby enabling precise formation of memory trenches and word lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of stacks is increased to enhance memory capacity, then memory capacity is improved, but fine patterning becomes difficult due to mask layer deformation

Engineering Contradiction:
Improvememory capacityVSAvoidfine patterning precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent divides the single mask layer into multiple mask layers (first mask layer and second mask layer) with different functions. The first mask layer forms initial patterns, while the second mask layer forms intersecting patterns, allowing complex three-dimensional structures to be created through sequential patterning steps without requiring excessively fine single-step patterning

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional planar patterning to three-dimensional stacked patterning by forming mask layers at different heights and orientations. The intersecting mask layers create vertical and horizontal patterns that define the three-dimensional memory cell structure, enabling increased storage density through vertical stacking

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the number of stacks is increased to enhance memory capacity, then memory capacity is improved, but etching configuration control becomes difficult

Engineering Contradiction:
Improvememory capacityVSAvoidetched configuration precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The etching process is segmented into multiple sequential steps, each controlled by a specific mask layer. The first etching step creates initial trenches guided by the first mask layer, followed by a second etching step that creates intersecting structures guided by the second mask layer, allowing precise control of complex three-dimensional etching configurations

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first mask layer and first etching step are performed as preliminary actions to create the basic structural framework before the second mask layer is formed. This preliminary structuring simplifies subsequent patterning steps and ensures that the final three-dimensional configuration is achieved with high precision

Inventive Principle:
Principle #10Preliminary action

3Strength

If mask layer thickness is increased to maintain etching resistance, then etching resistance is improved, but mask layer deformation increases

Engineering Contradiction:
Improveetching resistanceVSAvoidmask layer shape stability
Core Design Contradiction:
StrengthVSShape

Solution Approach 1:

The mask layer system is segmented into multiple thinner layers rather than using a single thick mask layer. Each mask layer has optimized thickness sufficient for its specific etching step, maintaining adequate etching resistance while avoiding the deformation issues associated with excessively thick single mask layers

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first mask layer acts as an intermediary structure that is partially removed during the etching process to form the final pattern. This intermediary approach allows the mask to provide necessary structural support and etching resistance during processing while being designed to be selectively removed to achieve the desired final configuration

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10325920B2Method for manufacturing semiconductor device
Publication Date: 2019.06.18 KIOXIA CORP
  • US10325920B2 patent drawing
  • US10325920B2 patent drawing
  • US10325920B2 patent drawing

AI summary

A method for manufacturing a semiconductor device includes forming a first mask layer having a first opening on an underlying layer; forming a first layer in a space where the underlying layer is selectively removed via the first opening; forming a second mask layer on the first mask layer and the first layer, the second mask layer having a second opening crossing the first opening; and selectively removing the first layer at a portion where the first opening and the second opening cross. At least one of the first and second mask layers having openings including the first or second opening, the openings being arranged in the first mask layer along a first direction, and/or being arranged in the second mask layer along a second direction, the first opening crossing the second opening in the first direction, and the second opening crossing the first opening in the second direction.