SRAM Bitline Architecture Using Vertical Gate-All-Around Transistors
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Solution Overview
Problem
As the semiconductor industry advances to nanometer technology nodes, challenges in fabrication and design lead to the need for improved bitline architecture in SRAM arrays, particularly in three-dimensional designs like Fin FET and gate-all-around devices, to achieve higher density, performance, lower power consumption, and reduced costs.
Innovation Solution
The proposed solution involves a layout structure for an SRAM array using vertical gate-all-around (VGAA) transistors with a small unit cell area, featuring a unique bitline architecture where bitlines are formed by connected source active regions and metal layers, reducing resistance and coupling capacitance, and utilizing VGAA transistors to control short channel effects and lower power operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional bitline architecture is used in SRAM arrays, then layout simplicity is maintained, but resistance is high and coupling capacitance is increased
Solution Approach 1:
The patent transitions from planar bitline architecture to a three-dimensional configuration where bitlines are formed at different vertical levels. Specifically, first bitlines are formed at a first level and second bitlines are formed at a second level, allowing spatial separation that reduces coupling capacitance while maintaining electrical connectivity through vertical vias. This dimensional change enables lower power consumption without excessive layout complexity.
2Productivity
If SRAM unit cell area is reduced for higher density, then device density increases, but short channel effects become more severe
Solution Approach 1:
The patent employs vertical gate-all-around (VGAA) transistors where the gate structure extends vertically to surround the channel from all directions. This three-dimensional gate configuration provides superior electrostatic control over the channel, effectively suppressing short channel effects even when the unit cell area is reduced to increase device density.
Solution Approach 2:
The VGAA transistor structure utilizes composite material layers including gate dielectric materials and conductive gate materials arranged in a vertical stack. This composite structure enables enhanced gate control efficiency and improved short channel effect suppression while maintaining compact unit cell dimensions for high-density SRAM arrays.
3Power
If VGAA transistors are used, then short channel effects are controlled and power consumption is reduced, but fabrication complexity increases
Solution Approach 1:
The patent segments the SRAM array into multiple subarrays with systematic bitline assignments. First bitlines are assigned to first subarrays and second bitlines to second subarrays, allowing modular fabrication approaches. This segmentation enables VGAA transistor fabrication to be performed in a structured manner, reducing overall fabrication complexity while maintaining the power consumption benefits of VGAA devices.
Data Source
AI summary
A column of a static random access memory (SRAM) array includes a first subarray including a first plurality of SRAM cells and a second subarray including a second plurality of SRAM cells. Each of the first and second plurality of SRAM cells includes first through fourth source active regions by which source regions of transistors thereof are formed. The column of the SRAM array includes a first bitline formed by the third source active regions of the first plurality of SRAM cells, a second bitline formed by the third source active regions of the second plurality of SRAM cells and spaced apart from the first bitline, and a third bitline formed by a metal layer extending over the third source active regions of the first and second plurality of SRAM cells and electrically connected to the second bitline but not to the first bitline.