Active Matrix Substrate Interconnects for Narrow Frame Design
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Solution Overview
Problem
Conventional active matrix substrates face challenges in frame narrowing due to the large area occupied by interconnects and protective circuitry, which increases the size of the frame and makes it difficult to reduce the interconnect area, leading to issues with electrostatic discharge and the need for protective circuitry.
Innovation Solution
The active matrix substrate design features interconnects with varying sheet resistances and configurations, including a first interconnect layer with a low sheet resistance and a second interconnect layer with a higher sheet resistance, connected by a connection section, which allows for narrower interconnect pitches and eliminates the need for protective circuitry by using the higher resistance as a protective measure against electrostatic discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If interconnects are arranged in a narrowing fan shape to reduce frame size, then the interconnect area is reduced, but the interconnect length becomes shorter making it more difficult to omit protective circuitry
Solution Approach 1:
The patent changes the electrical resistance parameter of the interconnect by using a high-resistance interconnect layer instead of a low-resistance one. This parameter change allows the interconnect to function as both a signal transmission path and an electrostatic discharge protection mechanism, eliminating the need for separate protective circuitry even when interconnect length is reduced due to fan-shaped arrangement
Solution Approach 2:
The interconnect structure is designed to perform multiple functions simultaneously: signal transmission and electrostatic discharge protection. By incorporating a high-resistance interconnect layer, the same interconnect that transmits signals also provides protection against electrostatic discharge, eliminating the need for separate protective circuitry
2Reliability
If protective circuitry is added to prevent electrostatic discharge, then reliability is improved, but the frame size increases
Solution Approach 1:
The patent merges the electrostatic discharge protection function into the interconnect structure itself by adding a high-resistance interconnect layer. This combines the signal transmission function and the protection function into a single integrated structure, eliminating the need for separate protective circuitry and reducing overall frame size
Solution Approach 2:
The interconnect structure provides its own electrostatic discharge protection through the high-resistance layer without requiring external protective circuitry. The high-resistance interconnect layer inherently limits electrostatic discharge current, allowing the interconnect to protect itself
3Measurement precision
If interconnect pitch is narrowed to increase resolution, then display resolution is improved, but electrostatic discharge protection becomes more difficult to implement
Solution Approach 1:
The patent changes the resistance parameter of the interconnect layer to high resistance, which enables electrostatic discharge protection even when interconnect pitch is narrowed. The high resistance limits discharge current effectively regardless of the reduced spacing between interconnects
Solution Approach 2:
The patent uses a composite interconnect structure with multiple layers having different resistance characteristics. The high-resistance interconnect layer is specifically designed to provide electrostatic discharge protection while coexisting with low-resistance layers for signal transmission, enabling both narrow pitch and reliable protection
Data Source
AI summary
Interconnects (34) include an inside interconnect section (40) and an outside interconnect section (41). The inside interconnect section (40) includes a first interconnect layer (42), a second interconnect layer (43), and a connection section (44) that connects the first interconnect layer (42) and the second interconnect layer (43). The outside interconnect section (41) includes a third interconnect layer (45). Of a plurality of interconnects (34), in one interconnect (X) of neighboring interconnects the second interconnect layer (43) and the third interconnect layer (45) are connected, and in another of the neighboring interconnects (Y), the first interconnect layer (42) and the third interconnect layer (45) are connected.