Dummy Flipflop Placement for Semiconductor Circuit Modification
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Solution Overview
Problem
Current semiconductor integrated circuit design methods require extensive modifications to both diffusion and interconnect layers during circuit modifications, leading to increased costs and development time, and can result in clock skew and signal integrity issues due to rerouting.
Innovation Solution
Incorporating a dummy flipflop connected in parallel to actual operation flipflops via power supply lines, allowing for minimal interconnect modifications without cell replacement, thereby reducing the number of layers modified and minimizing clock skew and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dummy cells are used and cell replacement is performed for circuit modification, then circuit modifiability is achieved, but both diffusion layer and interconnect layer must be changed, increasing mask cost and development time
Solution Approach 1:
The patent applies preliminary action by pre-placing dummy flipflops in the circuit design before fabrication. These dummy flipflops are positioned in advance at locations where future circuit modifications might be needed, allowing the circuit to be modified by simply activating pre-positioned elements rather than adding new cells later. This preliminary placement eliminates the need for costly post-fabrication mask changes to the diffusion layer.
2Adaptability or versatility
If interconnect rerouting is performed for circuit modification, then circuit functionality is updated, but clock skew may increase and signal integrity may deteriorate
Solution Approach 1:
The patent uses copying by creating dummy flipflops that are identical copies of actual flipflop cells. These dummy flipflops replicate the electrical characteristics and timing behavior of real flipflops, ensuring that when they are activated for circuit modification, the clock distribution network experiences minimal disturbance. The copied structure guarantees consistent signal integrity and clock skew characteristics.
Solution Approach 2:
The patent applies equipotentiality by placing dummy flipflops at locations that maintain balanced clock distribution. The dummy flipflops are positioned to achieve equal clock path lengths from the clock buffer to both actual and dummy flipflops, ensuring that clock skew remains minimized. This equipotential placement strategy prevents timing violations when circuit modifications are made.
3Area of stationary object
If the distance between clock terminals is reduced for dummy flipflop placement, then layout density is improved, but clock skew control becomes more challenging
Solution Approach 1:
The patent applies local quality by adjusting the clock terminal positioning strategy based on local layout conditions. Dummy flipflops are placed with their clock terminals at specific distances from the clock buffer, optimizing both density and timing. The local quality principle allows different regions of the circuit to have different dummy flipflop placements tailored to their specific timing and density requirements.
Data Source
AI summary
The semiconductor integrated circuit of the invention includes: two first power supply lines placed in parallel in a same interconnect layer; a second power supply line placed between the two first power supply lines in the same interconnect layer; an actual operation flipflop connected to one of the two first power supply lines and the second power supply line and having a first clock terminal; and a dummy flipflop connected to the other first power supply line and the second power supply line and having a second clock terminal. The dummy flipflop includes: a contact connected to the other first power supply line or the second power supply line; and an interconnect for connecting the second clock terminal with the contact.