Multilevel Wiring Power Gating for Semiconductor Miniaturization
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Solution Overview
Problem
The existing semiconductor device configurations using power gating techniques face challenges with miniaturization, leading to increased resistance in power supply lines due to limited occupied regions, which restricts further reduction in cell array size and affects circuit performance.
Innovation Solution
The semiconductor device employs a configuration with multiple circuit cell arrays, each supplied with different power voltages, utilizing main and pseudo power supply lines with driver transistors to manage voltage states, allowing for increased power supply line width and reduced wiring resistance, enabling efficient power management and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of the cell array in the height direction is reduced through miniaturization, then the integration density is improved, but the regions that can be occupied by the power supply lines are reduced, leading to increased resistance
Solution Approach 1:
The patent transitions from a single-plane power supply arrangement to a three-dimensional multilevel wiring structure. Power supply lines are distributed across multiple wiring layers (first wiring layer, second wiring layer, third wiring layer) with vertical connections via contact holes and plug structures. This dimensional expansion allows sufficient power delivery capability while maintaining reduced cell array footprint.
Solution Approach 2:
The power supply network is segmented into multiple independent wiring layers, each carrying specific power supply lines (e.g., first power supply line, second power supply line, third power supply line). This segmentation allows optimized routing and width allocation for each power line independently, reducing overall resistance while adapting to the miniaturized cell array geometry.
2Adaptability or versatility
If multiple power supply lines are arranged in a single cell array, then power gating functionality is achieved, but the occupied region for power supply lines increases, limiting further miniaturization
Solution Approach 1:
Multiple power supply lines required for power gating are arranged across multiple wiring layers instead of competing for horizontal space in a single layer. The first power supply line is in the first wiring layer, while the second and third power supply lines are in the second wiring layer, with vertical interconnections. This releases horizontal space for circuit cell miniaturization while maintaining full power gating functionality.
Solution Approach 2:
The power supply network is nested across multiple wiring layers, with each layer containing subsets of the required power lines. The first wiring layer contains the first power supply line, while the second wiring layer contains the second and third power supply lines. This nested arrangement efficiently packs multiple power lines into a compact vertical structure, reducing the horizontal footprint.
3Reliability
If the width of power supply lines is increased to reduce resistance, then the power delivery capability is improved, but the occupied area increases, affecting circuit integration density
Solution Approach 1:
The patent distributes power supply lines across multiple wiring layers with vertical connections, effectively increasing the cross-sectional area for power delivery without increasing the planar footprint. The first power supply line in the first wiring layer and the second/third power supply lines in the second wiring layer work together to provide enhanced current carrying capacity while maintaining compact integration.
Solution Approach 2:
Multiple power supply lines from different wiring layers are merged to form a composite power delivery network. The first power supply line (first wiring layer) and the second power supply line (second wiring layer) are combined through vertical interconnections to provide redundant and enhanced power delivery paths, achieving low resistance without requiring any single line to be excessively wide.
Data Source
AI summary
A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively.