Stacked Gate Non-Volatile Memory Cell Structure
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Solution Overview
Problem
As semiconductor devices are miniaturized to increase memory density, the reduced gate length leads to abnormal punch-through and wear of the tunneling oxide layer, affecting electrical performance and reliability of non-volatile memory cells.
Innovation Solution
A non-volatile memory with a stacked gate structure featuring a floating gate, tunneling dielectric layer, erase gate dielectric layer, assist gate dielectric layer, and a control gate, where the floating gate has a corner portion covered by the erase gate, allowing for reduced operating voltage and increased coupling ratio, thereby enhancing reliability and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate length is reduced to increase memory density, then the density of the non-volatile memory is improved, but abnormal punch-through occurs between source and drain and the tunneling oxide layer wears out
Solution Approach 1:
The gate structure is segmented into multiple components: control gate, erase gate, and assist gate arranged in a stacked configuration. This segmentation allows each gate to perform specific functions with optimized voltage application, preventing punch-through effects while maintaining high density
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional stacked gate structure. By stacking gates vertically (control gate, erase gate, assist gate), the design achieves higher density without further reducing gate length, thereby avoiding the punch-through problem associated with scaled-down lateral dimensions
2Quantity of substance
If the gate length is reduced to increase memory density, then the density of the non-volatile memory is improved, but the tunneling oxide layer experiences wear from repeated electron passage
Solution Approach 1:
The tunneling function is segmented and distributed across multiple gates (control gate, erase gate, assist gate) rather than relying on a single gate structure. This distribution reduces the stress and wear on the tunneling oxide layer by spreading electron passage events across multiple controlled interfaces
Solution Approach 2:
The assist gate acts as an intermediary element that helps control electron flow and electric field distribution. By introducing this intermediate gate structure, the patent reduces direct stress on the tunneling oxide layer during programming and erasing operations
3Reliability
If the overlap area between floating gate and control gate is increased to improve gate coupling ratio, then the operating voltage and efficiency are improved, but the device area increases reducing density
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple gates (control gate, erase gate, assist gate) above each other. This three-dimensional arrangement achieves high gate coupling ratio without increasing the lateral overlap area, thereby maintaining high memory density while improving electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables operation at lower voltages, increases memory density, and improves the speed and reliability of data erasure by concentrating the electric field and reducing wear on the tunneling oxide layer.
Implementation Method 1
The tunneling dielectric layer is disposed between the floating gate and the substrate
Implementation Method 2
the floating gate has a corner portion covered by the erase gate, allowing for reduced operating voltage and increased coupling ratio, thereby enhancing reliability and density
Data Source
AI summary
A non-volatile memory having memory cells is provided. A stacked gate structure has gate dielectric layer, assist gate, insulation layer, and erase gate disposed in order. The floating gate is disposed on a first sidewall of the stacked gate structure, the floating gate has a corner portion at the top portion, and erase gate covers the corner portion. The tunneling dielectric layer is disposed under the floating gate. The erase gate dielectric layer is disposed between the erase gate and the floating gate. The assist gate dielectric layer is disposed between the assist gate and the floating gate. The source region and the drain region are respectively disposed at two sides of the stacked structure and the floating gate. The control gate is disposed on the source region and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate.