Semiconductor Gate Electrode Reinforcement and Parasitic Capacitance Reduction
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Solution Overview
Problem
In NAND memories, the miniaturization of semiconductor integrated circuits leads to disturbances due to parasitic capacitance and error writing caused by low dielectric constant interlayer films between gate electrodes, resulting in malfunction as gate length decreases to 30 nm to 20 nm.
Innovation Solution
A semiconductor memory device with a reinforced insulation film extending orthogonally to connect adjacent gate electrodes and an interlayer dielectric film with voids between them, physically supporting the gate electrodes and reducing parasitic capacitance by using a specific manufacturing method involving multiple dielectric films and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interlayer dielectric films with low dielectric constant (PSZ, HDP-CVD, BPSG) are used to fill between adjacent gate electrodes, then the manufacturing process is simple and materials are readily available, but parasitic capacitance between adjacent floating gate electrodes increases causing threshold variation and control electrode disturbance
Solution Approach 1:
The patent introduces a porous low-k dielectric material as the interlayer dielectric film filling between adjacent gate electrodes. This porous structure reduces the dielectric constant compared to conventional solid dielectric materials (PSZ, HDP-CVD, BPSG), thereby decreasing parasitic capacitance between adjacent floating gate electrodes and preventing control electrode disturbance while maintaining manufacturing feasibility
Solution Approach 2:
The patent employs a composite structure combining the porous low-k dielectric interlayer film with reinforced insulation films having different dielectric constants. This composite material approach allows optimization of both parasitic capacitance reduction and mechanical strength, addressing the contradiction between reliability improvement and manufacturing simplicity
2Productivity
If gate length is miniaturized to 30 nm to 20 nm to progress semiconductor integration, then device density increases, but disturbances from parasitic capacitance and error writing increase causing malfunction
Solution Approach 1:
The porous low-k dielectric material is specifically designed for miniaturized gate structures (30 nm to 20 nm gate length). The porous structure provides sufficient insulation between adjacent gates at ultra-fine dimensions, preventing error writing and control electrode disturbance while enabling high device density through continued miniaturization
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant) of the interlayer film by using porous low-k material. This parameter change reduces parasitic capacitance effects that become critical at 30 nm to 20 nm gate lengths, allowing high-density integration without sacrificing reliability
3Strength
If interlayer dielectric film is deposited to fill between adjacent gate electrodes, then structural support is provided, but dishing occurs during flattening process
Solution Approach 1:
The patent uses a composite structure of porous low-k dielectric interlayer film combined with reinforced insulation films. The reinforced insulation films provide mechanical strength and structural support, while the porous low-k material fills the spaces between gates. This composite approach prevents dishing during flattening while maintaining the low parasitic capacitance benefits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses disturbances from parasitic capacitance and error writing, preventing gate electrode destruction and maintaining device functionality even at high aspect ratios, while also preventing dishing during interlayer dielectric film flattening.
Implementation Method 1
a disturbance (threshold variation) due to a parasitic capacitance between adjacent floating gate electrodes
Implementation Method 2
physically supporting the gate electrodes and reducing parasitic capacitance
Implementation Method 3
A specific dielectric constant of each of these interlayer dielectric films is relatively low
Data Source
AI summary
A semiconductor memory device includes gate electrodes extending in a first direction above a surface of a substrate. The semiconductor memory device also includes a reinforcement insulation film formed in a line shape and extending in a second direction crossing the gate electrodes in a plane view viewed from above the surface of the substrate, and connected to adjacent gate electrodes. Further, the semiconductor memory device includes an interlayer dielectric film provided between the adjacent gate electrodes, and having a void inside.