Resistance Variable Memory Write Pulse Control Circuit
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Solution Overview
Problem
Resistance variable memory devices, particularly phase changeable RAM (PCRAM), experience snapback and overshoot currents during memory cell turn-on, leading to malfunctions and transient currents in adjacent cell groups due to characteristics of the resistance layer, causing instability in memory operations.
Innovation Solution
A resistance variable memory device with a control circuit block that includes a write pulse control block with high resistance path and bypass circuits, which selectively connects with the global word line to reduce transient currents by managing the resistance path based on detection signals and address information, ensuring minimal voltage and current are supplied before turn-on and normal voltage and current after turn-on to minimize snapback and overshoot currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory cell is turned on using conventional resistance variable memory structure, then the memory cell can be accessed and operated, but transient currents (snapback, overshoot, and spike currents) are generated causing malfunctions and instability
Solution Approach 1:
The patent introduces a current control circuit as an intermediary component between the word line and the memory cell array. This control circuit actively monitors and regulates the current flowing to memory cells, particularly those adjacent to the control circuit block, to prevent transient currents (snapback, overshoot, and spike currents) from causing malfunctions. The current control circuit acts as a mediator that suppresses harmful transient effects while maintaining normal memory cell operation.
2Ease of operation
If voltage and current are supplied to turn on a memory cell, then the memory cell can be activated, but snapback and overshoot currents are generated during turn-on
Solution Approach 1:
The patent implements preliminary action by using a detection circuit to identify when a memory cell is about to turn on, and a current control circuit to pre-regulate the current before the actual turn-on occurs. The current control circuit is activated in advance to suppress snapback and overshoot currents during the turn-on transition, preventing these harmful effects before they can cause malfunctions in the memory cell or adjacent cells.
3Productivity
If memory cells are arranged in a cross point array structure, then memory density and access efficiency are improved, but transient currents affect adjacent cell groups causing malfunctions
Solution Approach 1:
The patent applies local quality by implementing a current control circuit that specifically targets and regulates current to memory cells adjacent to the control circuit block, rather than uniformly controlling all memory cells. This localized current control approach addresses the specific problem of transient currents affecting adjacent cell groups in the cross point array structure, while maintaining the high-density and efficient access characteristics of the cross point architecture.
Data Source
AI summary
A resistance variable memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and a selected memory cell. The write pulse control block may selectively enable any one of the high resistance path circuit and the bypass circuit in accordance with a position the selected memory cell.