Single-Layer Semiconductor Channel for 3D Memory
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Solution Overview
Problem
The interface between dual semiconductor channel layers in vertical memory devices generates interface states that scatter charge carriers, reducing mobility and on-current in vertical memory devices.
Innovation Solution
A method involving the formation of a stack of alternating insulating and spacer material layers, followed by anisotropic etching to expose semiconductor surfaces, and deposition of a semiconductor channel layer directly on the tunneling dielectric layer, which includes an ONO stack and silicon nitride, to minimize charge scattering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual layer semiconductor channel is employed to protect the tunneling dielectric during anisotropic etching, then the tunneling dielectric is protected from damage, but interface states are generated at the interface between the two semiconductor channel layers, reducing charge carrier mobility and on-current
Solution Approach 1:
The patent removes the first semiconductor channel layer that was previously deposited before the anisotropic etch. By eliminating this layer, the interface between two semiconductor channel layers is removed, thereby eliminating the interface states that scattered charge carriers and reduced mobility. The tunneling dielectric is still protected during etching through alternative means (direct deposition on substrate without requiring a protective semiconductor layer).
Solution Approach 2:
The patent segments the deposition process into two distinct stages: (1) anisotropic etching of the memory film to expose the semiconductor substrate, and (2) subsequent deposition of the semiconductor channel layer directly on the exposed substrate. This segmentation allows the tunneling dielectric to be protected during etching while avoiding the creation of a harmful interface by depositing the channel material directly on the substrate rather than on another semiconductor layer.
2Reliability
If a first semiconductor channel layer is deposited prior to anisotropic etch over the tunneling dielectric, then the tunneling dielectric is protected during etching, but the interface between channel layers generates interface states that reduce on-current
Solution Approach 1:
The patent extracts/removes the first semiconductor channel layer from the process sequence. This elimination prevents the formation of the interface between two semiconductor channel layers, thereby preventing the generation of interface states that would reduce on-current. The tunneling dielectric protection function is maintained through the etching process by directly exposing the substrate and controlling the etching parameters.
Solution Approach 2:
The patent performs the anisotropic etching of the memory film to expose the semiconductor substrate before depositing the semiconductor channel layer. This preliminary action sequence ensures that the tunneling dielectric is protected during etching (by not having a semiconductor layer on it to damage) while avoiding the creation of a harmful interface. The channel layer is then deposited directly on the exposed substrate in a subsequent step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge carrier mobility and on-current in vertical memory devices by reducing interface states and optimizing the semiconductor channel structure.
Implementation Method 1
tunneling dielectric layer, which includes an ONO stack and silicon nitride
Implementation Method 2
A semiconductor channel layer is deposited directly on the tunneling dielectric layer
Implementation Method 3
enhances charge carrier mobility and on-current in vertical memory devices by reducing interface states
Data Source
AI summary
A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed through the alternating stack. A memory material layer, a tunneling dielectric layer, and a silicon oxide liner are formed in the memory opening. A sacrificial liner is subsequently formed over the tunneling dielectric layer. The layer stack is anisotropically etched to physically expose a semiconductor surface of the substrate underneath the memory opening. The sacrificial liner may be removed prior to, or after, the anisotropic etch. The silicon oxide liner is removed after the anisotropic etch. A semiconductor channel layer can be deposited directly on the tunneling dielectric layer as a single material layer without any interface therein.