Memory Device Split Gate Structure High-K Metal Gate Fabrication

The patent applies preliminary action by forming the metal gate electrode structure before the final gate patterning step. The metal gate is initially formed as a continuous layer covering the entire channel region, and then selectively removed in later steps to form the final gate pattern. This approach simplifies the manufacturing process by avoiding the need for complex alignment and patterning steps that would be required if the metal gate were formed directly in its final pattern.

The patent employs inversion by reversing the conventional sequence of gate formation. Instead of forming the gate pattern first and then filling it with metal, the metal is deposited first as a continuous layer and then selectively removed. This inverted approach reduces manufacturing complexity by using simpler deposition processes followed by selective removal, rather than requiring precise patterning and filling operations.

The patent applies universality by using the same metal layer formation process for multiple gate structures (control gates and select gates) in the flash memory device. The metal gate electrode layer is formed continuously across different functional regions, and then selectively patterned to create different gate structures. This multi-functional approach reduces manufacturing complexity by using a single deposition process serving multiple purposes, rather than requiring separate processes for each gate type.

The patent merges the formation of multiple gate structures into a single continuous metal layer deposition step. Instead of forming control gates and select gates separately, the metal gate electrode is deposited as one continuous layer that subsequently gets selectively removed and patterned to create the final gate structure. This combining approach reduces the total number of manufacturing steps and improves functional density.

The patent applies parameter changes by transitioning from polysilicon gate material to metal gate material, and from thick gate structures to thinner gate structures. The metal gate electrode enables smaller feature sizes and improved device performance while maintaining manufacturing simplicity through the use of standard sputtering deposition processes. The continuous metal layer formation followed by selective removal allows for precise control of gate dimensions at scaled feature sizes.

The patent substitutes the conventional polysilicon gate material and thick gate structure with metal gate material and thinner gate structure. This material substitution enables improved device performance and scaling while the adopted process (continuous deposition followed by selective removal) maintains manufacturing simplicity by using well-established thin film deposition techniques rather than requiring complex new process equipment.