Flash Memory Conductive Spacers for Cell Isolation
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Solution Overview
Problem
As semiconductor devices become more integrated, the interference phenomenon between neighboring cells in NAND flash memory devices increases due to reduced distance, leading to threshold voltage distribution failures, and the self-aligned shallow trench isolation (SA-STI) process becomes less effective with decreasing cell size.
Innovation Solution
A method of manufacturing flash memory devices that forms a floating gate using a single conductive layer without the SA-STI process, ensuring a sufficient distance between cells and increasing the coupling ratio by etching an isolation film at a predetermined thickness, while preventing damage to the tunnel oxide film and semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between cells is reduced to increase integration level, then the integration density is improved, but the interference phenomenon between neighboring cells increases
Solution Approach 1:
The patent divides the cell structure into distinct segments by introducing conductive spacers that physically separate neighboring cells. The spacers create isolated regions around each cell component, preventing electrical interference while maintaining high integration density through vertical stacking and compact lateral arrangement.
Solution Approach 2:
The conductive spacers act as intermediary elements positioned between neighboring cells. These spacers serve as electrical shields that block interference signals from propagating between adjacent cells, enabling closer cell spacing without sacrificing signal integrity or increasing interference.
2Ease of manufacture
If the SA-STI process is used to form isolation films, then the manufacturing process is simplified, but the alignment margin is reduced as cell size decreases
Solution Approach 1:
The patent employs self-aligned processes where the conductive spacers are formed automatically in registration with existing cell structures through conformal deposition and anisotropic etching. This self-alignment mechanism eliminates the need for additional photolithography alignment steps, maintaining process simplicity while achieving precise positioning even at reduced cell dimensions.
3Reliability
If the isolation film thickness is increased to control effective field height, then the coupling ratio is improved, but the tunnel oxide film may be damaged during etching
Solution Approach 1:
The patent performs preliminary protective actions by forming a carefully controlled isolation film thickness that provides sufficient effective field height control while maintaining a safety margin below the tunnel oxide film depth. This preventive approach ensures that subsequent etching processes to form conductive spacers do not penetrate deep enough to damage the tunnel oxide, eliminating the need for complex protective measures during etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes interference between neighboring cells, enhances the coupling ratio, and prevents damage during the etching process, effectively addressing the limitations of high-integration semiconductor devices.
Implementation Method 1
A NAND flash memory device performs data program by injecting electrons into the floating gate by Fowler-Nordheim (FN) tunneling phenomenon
Data Source
AI summary
A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacturing process of highly integrated semiconductor devices. It is therefore possible to minimize interference between neighboring cells.