Vertical Thin Film Transistor Single Patterning Alignment
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Solution Overview
Problem
The manufacturing process of vertical type thin film transistors (TFTs) is complicated, leading to poor alignment accuracy and high production costs, which affects the yield and resolution of display panels.
Innovation Solution
A simplified manufacturing method for TFTs is introduced, where a first electrode, isolating layer, active layer, and gate insulating layer are formed on a base substrate, and a second electrode and gate electrode are simultaneously formed in the same layer using a single patterning process, reducing the number of process steps and improving alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes are used to form electrodes and insulating layers separately, then each layer can be formed with precise control, but the manufacturing process becomes complicated and alignment accuracy deteriorates
Solution Approach 1:
The patent combines the formation of the second electrode and gate electrode into a single patterning process step. By forming both electrodes simultaneously in the same layer using one patterning process, the manufacturing process complexity is reduced while maintaining alignment accuracy between the electrodes. This merging of operations directly addresses the contradiction by eliminating multiple sequential patterning steps that would otherwise complicate the process and potentially degrade alignment precision.
Solution Approach 2:
The single patterning process serves multiple functions: it defines the pattern for the second electrode, defines the pattern for the gate electrode, and establishes their relative positions simultaneously. This multi-functional approach replaces what would traditionally require separate patterning operations, thereby simplifying the manufacturing process while ensuring precise alignment between different electrode structures.
2Productivity
If traditional multi-step manufacturing process is used, then each component can be formed independently, but production efficiency decreases and costs increase
Solution Approach 1:
The patent merges the formation of multiple electrode structures into a single patterning process, reducing the total number of manufacturing steps. This consolidation increases production efficiency by minimizing the sequence of operations required and reduces manufacturing costs by decreasing material consumption, equipment usage time, and process complexity. The single patterning step simultaneously creates both the second electrode and gate electrode, directly improving productivity and ease of manufacture.
3Area of stationary object
If TFT size is reduced to improve pixel aperture ratio, then resolution improves, but manufacturing alignment becomes more difficult
Solution Approach 1:
By forming the second electrode and gate electrode in the same patterning step, the patent ensures that their relative positions are determined by a single alignment reference, eliminating cumulative alignment errors that would occur with multiple sequential patterning steps. This is particularly critical for small-sized TFTs where even minor misalignments can significantly impact device performance and pixel aperture ratio.
Solution Approach 2:
The patent positions the second electrode and gate electrode in the same layer (same dimensional plane), which simplifies the alignment requirements compared to traditional multi-layer approaches. By co-locating these electrodes in one layer formed by a single patterning process, the manufacturing precision requirement is relaxed while still achieving the desired small TFT footprint and high pixel aperture ratio.
Data Source
AI summary
A thin film transistor (TFT), a manufacturing method thereof, an array substrate and a display panel are disclosed. The manufacturing method includes: providing a base substrate; forming a first electrode, an isolating layer, an active layer and a gate insulating layer on the base substrate; simultaneously forming a second electrode and a gate electrode, wherein the second electrode is connected to the active layer.