3D Non-Volatile Memory Device With Local Insulation Adjustment
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Solution Overview
Problem
The semiconductor process for manufacturing non-volatile memory devices often results in structural non-uniformity, leading to decreased manufacturing yield and reduced storage capacity due to micro-fabrication challenges.
Innovation Solution
A non-volatile memory device design featuring a three-dimensional structure with a memory cell array that includes global bit lines, local bit lines, word lines, and control elements, where adjustment parts and outer electrodes are strategically placed to ensure uniform intervals and insulation, mitigating the micro-loading effect and improving manufacturing precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor process micro-fabrication is used to increase storage capacity, then degree of integration improves, but structural non-uniformity increases leading to decreased manufacturing yield
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to a three-dimensional structure where bit lines extend vertically through multiple layers. This dimensional change allows increased storage capacity while maintaining uniform insulation thickness through vertical stacking rather than horizontal scaling, thereby avoiding the structural non-uniformity problems associated with continued planar scaling.
Solution Approach 2:
The patent applies different insulation thicknesses to different spatial locations: thicker insulation is provided in regions where bit lines closely approach word lines or adjacent bit lines, while thinner insulation suffices in other regions. This localized quality adjustment ensures reliable electrical insulation without requiring uniform thick insulation throughout, thus maintaining manufacturing precision while enabling high-density three-dimensional integration.
2Quantity of substance
If three-dimensional memory structure is implemented, then storage capacity increases, but manufacturing complexity increases due to multiple layers and interconnections
Solution Approach 1:
The patent divides the memory structure into multiple discrete layers with bit lines extending vertically through them, allowing independent formation and control of each layer. This segmentation enables systematic manufacturing processes where each layer can be processed separately, reducing the complexity of creating the entire three-dimensional structure in one step while still achieving high storage capacity through vertical stacking.
Solution Approach 2:
The bit lines serve multiple functions: they act as electrical conductors for data transmission, provide structural framework for the three-dimensional architecture, and enable vertical integration of multiple memory layers. This multi-functionality reduces the need for separate components and simplifies the overall manufacturing process despite the increased three-dimensional complexity.
3Reliability
If uniform insulation thickness is maintained in three-dimensional structure, then electrical breakdown risk reduces, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements variable insulation thickness tailored to specific spatial locations: thicker insulation is applied where bit lines closely approach word lines or adjacent bit lines to prevent electrical breakdown, while thinner insulation is used in regions with sufficient spacing. This localized quality approach maintains electrical insulation reliability without requiring uniform high-precision thickness control throughout the entire structure, thereby reducing overall manufacturing precision requirements.
Data Source
AI summary
According to an embodiment, a non-volatile memory device includes a first interconnection extending in a first direction, a plurality of second interconnections provided side by side on the first interconnection and extending in a second direction intersecting the first direction and a memory layer provided on a side surface of each second interconnection. The device also includes a control element provided between each of the second interconnections and the first interconnection, an element part extending in the second direction, and a control electrode facing a side surface of the element part via a first insulating film. An adjustment part is provided on the first interconnection and adjacent to a control element connected to a second interconnection disposed at an end position of the second interconnections arranged in the first direction, and a first outer electrode provided between the adjustment part and the control element disposed at the end position.