3D Non-Volatile Memory Passive Devices Vertical Integration
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Solution Overview
Problem
Current 3D stacked non-volatile memory devices face challenges in reducing size due to space consumption between subarrays, which affects the efficiency of power and control signal routing, and the integration of peripheral circuitry such as resistors and capacitors is inefficient, leading to increased chip size.
Innovation Solution
The implementation of a space-efficient interconnect structure using insulation-filled slits and memory holes to connect lower and upper metal layers directly, eliminating the need for transfer and hookup areas between subarrays, and the use of stacked layers of conductive and dielectric materials to form passive devices like capacitors and resistors in a vertical arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional interconnect structures with transfer and hookup areas are used between subarrays, then signal routing is achieved, but the overall device size increases
Solution Approach 1:
The patent transitions from planar interconnect routing to vertical 3D stacking, where lower and upper metal layers are connected through vertical vias and insulation-filled structures. This dimensional change eliminates the need for lateral transfer and hookup areas, directly reducing device footprint while maintaining signal routing functionality.
Solution Approach 2:
The patent implements nested structures where insulation material is placed within etched slits and vias, and multiple conductive layers are stacked within a compact vertical space. This nesting approach maximizes space utilization and eliminates wasted lateral space, directly addressing the contradiction between compact size and routing complexity.
2Area of stationary object
If peripheral circuitry such as resistors and capacitors is integrated using conventional methods, then functional requirements are met, but chip size increases
Solution Approach 1:
The patent integrates passive components like resistors and capacitors in the vertical dimension using stacked conductive and dielectric layers, rather than spreading them out laterally. This vertical integration dramatically reduces the peripheral area required while maintaining full functional capability for signal conditioning and power management.
Solution Approach 2:
The patent creates a universal stacked layer structure that can serve multiple functions: signal routing through metal layers, capacitance through dielectric stacks, and resistance through patterned conductive paths. This multi-functional approach eliminates the need for separate dedicated areas for each component type, reducing overall chip size while maintaining versatility.
3Volume of moving object
If space-efficient interconnect structures are implemented, then device size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary patterning and insulation filling during the main fabrication sequence, preparing the vertical interconnect structures in advance before final metal deposition. This preliminary action simplifies subsequent manufacturing steps by pre-establishing the vertical pathways and insulation structures, reducing overall process complexity despite the advanced 3D architecture.
Data Source
AI summary
Passive devices such as resistors and capacitors are provided for a 3D non-volatile memory device. In a peripheral area of a substrate, a passive device includes alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are provided above the stack. Contact structures extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel, for a capacitor, or serially, for a resistor, by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers.