Solid-State Devices TRIZ Cases

An iPMA layer in a magnetoresistive stack increases anisotropy field strength, reducing write error rates during high-speed switching.

A light emitting device package connects opposite sidewalls with a molded reinforcing portion that reduces deformation while minimizing light blocking.

Through holes in a display panel conduct heat from light-emitting elements through the electrode layer to the substrate.

A page buffer circuit arranges bit lines at different levels with varying spaces to reduce coupling interference.

Segmented vias with an intervening passivation layer prevent lapping connection failures and undercut, lowering production costs.

A layered metal oxide field effect electrode combines thin metal strips with specific band gap films to enhance carrier mobility and light transmittance.

A semiconductor channel pad features a convex upper surface to enhance vertical transistor integration.

Porous silicon isolation traps carriers, reducing charge sharing from heavy ions and enhancing radiation hardening.

Vertical integration of stacked passive devices reduces peripheral area and chip size for 3D non-volatile memory.

Current sensors switch off output transistors during high current events by pulling down gate voltages before parasitic capacitance causes unintended switching.

A semiconductor storage apparatus fixes channel potentials via rear-side select gate transistors to isolate memory strings.

Merging first and second electrodes onto one base film with distinct conductor shapes reduces thickness and eliminates moiré patterns.

A thin film transistor array panel manufacturing method uses a unified conductive layer patterned with one photoresist mask to form data lines and pixel electrodes.

A sensor device uses barrier layers to suppress leakage currents in miniaturized piezoresistive elements.

A protective film connects discrete metal units with adhesive layers to encapsulate display panels simultaneously.

An optical grid structure with an air layer and capping film isolates adjacent color filters, reducing optical crosstalk while maintaining structural stability.

A thin film transistor design uses thinner active layer contact regions to lower electrical resistance at source and drain electrodes.

Dual polarizers and a transmission layer maintain external light polarization, preventing substrate reflection from lowering display contrast ratio.

A dual-substrate detection panel separates the light detection layer from the drive circuit to enable independent optimization of each component.

A nonvolatile ferroelectric perpendicular electrode cell uses a polymer thin film and serial PN diode switch.

Graded refractive layers in the transparent display area focus light through polyimide substrates, resolving low transmittance bottlenecks for clear imaging.

Graded density nitride and oxide layers in the interlayer insulator prevent internal layer breakage from external impacts while controlling warpage.

Concentrating electric fields on a dedicated conductive part reduces parasitic capacitance and eliminates the need for light-transmitting shielding layers.

Thin film transistor array substrate uses a channel protective film to shield the semiconductor layer.

Two-stage etching removes damaged electrode portions near dielectric edges to prevent reactive ion erosion and improve capacitor reliability.

A thin-film transistor array substrate uses a transparent pixel electrode and intermediate layer to form an organic light-emitting display.

A shielding electrode line blocks vertical electric fields to ensure accurate alignment of ultra-small light emitting devices.

A charge functional layer unifies the current path across an organic electroluminescence display panel to equalize voltage distribution.

Decoding circuitry replaces defective intermediate planes with redundant ones in 3D vertical channel memory stacks.

An electron-relay layer mediates charge transport between functional regions in a light-emitting element to enable efficient injection.

Segmenting the optical module into independently testable transmit and receive paths resolves thermal management challenges in compact pluggable transceivers.

A dual interface IC card uses electromagnetic induction to melt a bismuth-tin alloy, forming conductive bumps that join antenna terminals to micro module contacts.

Alternating band gap energy layers in tunnel insulation structures reduce charge loss and initial voltage shift while maintaining program erase speed.

Release paper mediator prevents surface tension convexity during LED encapsulation, improving light efficiency and reducing hot spots.

A display device slit uses an etch stop layer to form a stepwise side face in the bending area.

A stacked wafer structure bonds a CIS wafer to an ISP wafer using a lamination layer and through silicon vias.

A reinforcing bar suppresses deformation of the resin mask during deposition, preventing damage from misalignment in organic EL manufacturing.

Current sensing circuits feed back to the mirror controller, compensating for temperature variations to stabilize the micromirror opening angle.

Tapered blind holes in wafers guide solder flow during reflow to eliminate hemispherical ends and reduce package height.

A transflective layer with a higher refractive index than the first electrode enhances light reflection and resonance in OLED displays.

Direct bonding of inorganic glass members with embedded phosphors reduces thermal resistance and prevents resin deterioration.

A buried metal silicide pattern reduces electrical resistance between the P-N diode and word line in phase change memory devices.

A metal complex compound enables phosphorescent emission in organic light-emitting diodes.

Selective channel separation in diamond-shaped FinFETs reduces leakage current and junction capacitance while maintaining structural integrity.

A semiconductor device uses an offset p-type region to act as a ballast resistor for electrostatic discharge protection.

An electrostatic releasing element redirects charges from adjacent circuitry to prevent direct discharge, reducing defects during fabrication.

Partition structures separate contact holes from cathode deposition areas to prevent surface dents, ensuring uniform film thickness and high aperture rates.

Dual-layer spacers maintain uniform inner diameter to reduce contact area, resolving fabrication complexity in variable resistive memory devices.

Hexagon-shaped LEDs in circular reflective wells redirect light to boost extraction efficiency while enabling compact pixel arrangements.

Sublimation deposits perovskite layers in an inverted solar cell, eliminating solvent use and enhancing long-term air-stability.