3D NAND Memory Cell Array Select Gate Control for Interference Reduction
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Solution Overview
Problem
Current semiconductor storage apparatuses face challenges in reliable data reading operations due to interference from back opposite cells in three-dimensional NAND flash memory structures, leading to erroneous readings and reduced operation reliability.
Innovation Solution
The semiconductor storage apparatus employs a configuration where the select gate transistor in the rear-side memory string formation section is turned off during data reading, and the channel potential is fixed to a source line potential, preventing interference from back opposite cells by disconnecting the current path and ensuring accurate data differentiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data reading is performed in three-dimensional NAND flash memory structures, then storage capacity is improved, but interference from back opposite cells causes erroneous readings
Solution Approach 1:
The memory structure is divided into front-side and rear-side memory string formation sections, with separate select gate transistors for each section. This segmentation allows independent control of current paths, enabling the rear-side select gate transistor to be turned off during front-side reading operations, thereby preventing interference from back opposite cells while maintaining high storage capacity
Solution Approach 2:
The rear-side select gate transistor acts as an intermediary control element that prevents harmful current leakage from back opposite cells. By controlling the state of this intermediary transistor, the patent eliminates interference without affecting the normal reading operation of the front-side cells
2Reliability
If select gate transistor in rear-side memory string formation section is turned off, then interference from back opposite cells is prevented, but additional control complexity is introduced
Solution Approach 1:
The control signals for the select gate transistors in front-side and rear-side memory string formation sections are merged into a coordinated control scheme. The control circuit simultaneously manages both select gate transistors, turning off the rear-side transistor when reading from front-side cells, thereby achieving reliable interference prevention through integrated control rather than adding independent complex control mechanisms
Data Source
AI summary
A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.