Array Substrate Dual Via Structure for Contact Resistance
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Solution Overview
Problem
Conventional array substrates face issues with poor lapping connection and increased contact resistance in single deep-shallow hole designs, leading to manufacturing problems and reduced pixel aperture ratios, which increase production costs and display issues.
Innovation Solution
The array substrate design includes a first via and a second via with a conductive layer that penetrates the passivation and gate insulating layers, where the first via is positioned on the side of the second via, and the passivation layer partially extends between them, with a distance less than twice the photoresist layer etching fade distance, using materials like copper, aluminum, molybdenum, silicon oxide, and indium tin oxide, to improve the via structure and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single deep-shallow hole design is used to reduce occupied area and increase pixel aperture ratio, then the occupied area is reduced and aperture ratio is improved, but poor lapping connection and increased contact resistance occur
Solution Approach 1:
The via structure is segmented into two separate vias (first via and second via) instead of a single combined via. The first via penetrates the passivation layer and gate insulating layer to reach the first metal layer, while the second via only penetrates the passivation layer to reach the second metal layer. This segmentation allows each via to be optimized independently, avoiding the lapping connection problems that occur in single deep-shallow hole designs.
Solution Approach 2:
The gate insulating layer serves as an intermediary layer between the first via and the second via. The first via penetrates through the gate insulating layer to reach the first metal layer, while the second via stops at the gate insulating layer and connects to the second metal layer. This intermediary structure prevents direct etching of the gate insulating layer sidewalls that causes lapping connection problems.
2Area of stationary object
If a single deep-shallow hole design is used to increase pixel aperture ratio, then the aperture ratio is improved, but manufacturing precision deteriorates due to etching problems
Solution Approach 1:
The via formation process is segmented into two separate via formation steps. The first via is formed with controlled depth to penetrate the gate insulating layer and reach the first metal layer. The second via is formed with controlled depth to only penetrate the passivation layer and reach the second metal layer. This segmentation allows precise control of etching depth for each via, avoiding the manufacturing precision problems associated with single deep-shallow hole etching.
3Reliability
If dual-hole design is used to improve lapping connection, then connection quality is improved, but occupied area increases and aperture ratio decreases
Solution Approach 1:
The via structure transitions from a horizontal arrangement (dual-hole design with significant spacing) to a vertical stacking arrangement where the first via is positioned beneath the second via. The first via penetrates deeper to reach the first metal layer, while the second via connects to the second metal layer above. This vertical dimensionality change reduces the horizontal occupied area while maintaining the connection quality benefits of separate via structures.
Data Source
AI summary
An array substrate, a display panel and a method for manufacturing the array substrate are provided. The array substrate further includes a first via and a second via. A conductive layer fills the first via and the second via to electrically connect the first metal layer and the second metal layer. The first via is disposed on a side of the second via, and a passivation layer partially extends between the first via and the second via. The display panel includes the above-mentioned array substrate.