3D Vertical Channel Memory Word Line Repair via Redundant Planes
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Solution Overview
Problem
Current 3D memory devices with vertical channel structures face high costs due to the large area of defective word line blocks, which necessitate expensive replacement with 'good' blocks.
Innovation Solution
A memory device with a vertical channel structure that includes multiple stacks of conductive strips and additional intermediate planes, where decoding circuitry can replace defective intermediate planes with redundant ones, utilizing interlayer connectors and linking elements to maintain functionality and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a block is marked as bad due to a word line defect, then the memory device can continue operation using good blocks, but the cost increases due to the large area of the replaced block
Solution Approach 1:
The patent segments the word line structure into multiple intermediate planes (WL0-WLn) that can be independently replaced. Instead of replacing an entire block when a word line fails, only the defective intermediate plane needs to be swapped with a redundant one, significantly reducing the replacement area and cost while maintaining device reliability
Solution Approach 2:
The patent introduces an additional intermediate plane dimension for redundancy. By adding spare word line planes that can substitute for defective ones, the system enables localized repair without requiring full block replacement, thus resolving the contradiction between reliability and manufacturing cost
2Ease of repair
If additional intermediate planes are added for redundancy, then word line repair capability is improved, but the device complexity increases
Solution Approach 1:
The decoding circuitry is segmented into modular components that can independently select and activate specific intermediate planes. This modular approach allows the system to handle redundancy without proportionally increasing overall complexity, as each segment operates independently to manage its associated word line plane
Solution Approach 2:
The additional intermediate planes serve multiple functions: they can replace defective planes, provide backup capacity, and maintain structural symmetry. This multi-functionality justifies the added complexity by providing versatile repair and operational capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables cost-effective repair of defective word lines by using redundant planes, significantly reducing failure rates and maintaining device performance through efficient decoding and redundancy mechanisms.
Implementation Method 1
The memory device includes a stack of linking elements separated by insulating layers, and connected to conductive strips in respective intermediate planes in the plurality of intermediate planes (WLs) and to the additional intermediate plane
Implementation Method 2
In operation, when voltage is applied to a gate structure of a memory element via a word line (WL), a channel region in a memory cell in a vertical channel structure corresponding to the memory element beneath the gate structure is turned on
Data Source
AI summary
A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, a top plane of conductive strips, and an additional intermediate plane. A plurality of vertical structures is arranged orthogonally to the plurality of stacks. Memory elements are disposed in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of vertical structures. A stack of linking elements is connected to conductive strips in respective intermediate planes and to the additional intermediate plane. Decoding circuitry is coupled to the plurality of intermediate planes and the additional intermediate plane, and is configured to replace an intermediate plane indicated to be defective with the additional intermediate plane.