Page Buffer Circuit Bit Line Spacing for Coupling Interference
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Solution Overview
Problem
Conventional page buffer circuits in nonvolatile memory devices experience coupling interference due to the close proximity of bit lines, which affects data reading and storage efficiency.
Innovation Solution
The proposed page buffer circuit design includes bit lines arranged at different levels with varying spaces between them, utilizing selection transistors and sensing circuits to minimize coupling interference by controlling the spacing and level configuration of bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bit lines are arranged at the same level to simplify manufacturing, then ease of manufacture is improved, but coupling interference between adjacent bit lines increases
Solution Approach 1:
The patent applies dimensionality change by transitioning bit lines from a two-dimensional same-level arrangement to a three-dimensional multi-level structure. Bit lines are divided into first bit lines and second bit lines positioned at different vertical levels, with coupling interference reduction achieved through strategic spacing at each level. This spatial reconfiguration maintains manufacturing feasibility while effectively reducing capacitive coupling between adjacent bit lines.
2Area of stationary object
If bit lines are placed closer together to increase density, then area utilization is improved, but coupling interference increases
Solution Approach 1:
The invention utilizes vertical stacking to achieve three-dimensional bit line arrangement, allowing higher density without increasing lateral proximity. First and second bit lines are positioned at different levels, enabling compact area utilization while maintaining sufficient spacing between lines at each level to minimize coupling interference.
Solution Approach 2:
The patent implements local quality by applying different spacing strategies to bit lines at different levels. First bit lines and second bit lines have optimized spacing configurations tailored to their specific positions and coupling requirements, allowing dense overall arrangement while maintaining local spacing quality to reduce interference.
3Object-affected harmful factors
If spacing between bit lines is increased to reduce coupling interference, then coupling interference is reduced, but area occupied by bit lines increases
Solution Approach 1:
The patent resolves the area-expansion problem by moving the spacing dimension vertically. Instead of increasing lateral spacing between all bit lines, the invention positions first and second bit lines at different levels, achieving coupling interference reduction through vertical separation while maintaining compact lateral footprint.
Data Source
AI summary
A page buffer circuit includes first and second bit lines coupled to a first sensing circuit and with a first space therebetween, and third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween. The second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space.