ESD Protection Circuit With Current Sensor And Gate Pull-Down
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Solution Overview
Problem
Existing electrostatic discharge (ESD) protection circuits fail to prevent self-destruction of power transistors during high current ESD events, particularly in scenarios involving large power transistors with low ohmic routing, due to fast voltage transients causing parasitic base or gate capacitance pull-up and unintended switching.
Innovation Solution
A centralized clamp connected to the cathode of large isolation diodes or transistors, combined with lateral bipolar transistors forming current mirrors and a gate or base pull-down circuitry, which senses ESD current and prevents the output transistor from switching on by diverting the current and pulling down the gate or base, thereby preventing self-destruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard voltage clamp protection circuits are used, then the IC pin voltage is clamped below transistor breakdown voltage, but the power transistor can still switch on due to fast voltage transient pulling up the base or gate through parasitic capacitance
Solution Approach 1:
The patent introduces a mediator element (the ESD protection circuit with clamp transistor and diode) that intercepts and manages the ESD current before it can affect the power transistor. The clamp transistor acts as an intermediary that diverts the harmful current path, preventing the parasitic capacitance from pulling up the base/gate voltage of the power transistor during ESD events.
Solution Approach 2:
The protection circuit applies preliminary anti-action by preemptively clamping the voltage and diverting current during an ESD event before the parasitic capacitance can cause unintended switching. The fast-acting clamp transistor activates in response to voltage transients to counteract the harmful effect of charge injection into the power transistor's base or gate.
2Productivity
If large sized power transistors with low ohmic routing are used, then the ESD injected current can cause fast voltage transient, but this results in base or gate being pulled up through parasitic capacitance allowing the power transistor to switch on
Solution Approach 1:
The patent converts the harmful fast voltage transient caused by large power transistors during ESD into a beneficial signal. The clamp transistor detects the voltage transient and uses it to activate the protection mechanism, turning the harmful dV/dt event into a useful trigger for current diversion and preventing self-destruction.
3Reliability
If prior art ESD protection circuits are used, then voltage clamp is implemented, but the power transistor current from parasitic capacitance pull-up can still result in device destruction during high current ESD events
Solution Approach 1:
The patent segments the ESD protection function into distinct components: the clamp transistor for voltage clamping, the diode for current diversion, and the coordinated action for preventing power transistor switching. This segmentation allows each component to specialize in a specific aspect of ESD protection, with the clamp transistor handling voltage control and the diode handling current diversion, thereby providing comprehensive protection against both voltage breakdown and current-induced damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively prevents the output transistor from switching on and self-destructing during high current ESD events by diverting ESD current and controlling the gate or base pull-down circuitry, ensuring the protection of integrated circuits from damage.
Implementation Method 1
An electrostatic discharge (ESD) is a sudden unwanted current that can flow between two objects at different electrical potentials
Implementation Method 2
lateral bipolar transistors forming current mirrors which sense ESD current
Implementation Method 3
gate or base pull-down circuitry, which senses ESD current and prevents the output transistor from switching on by diverting the current and pulling down the gate or base
Data Source
AI summary
An electrostatic discharge (ESD) protection circuit for protecting one or more devices in an electronic circuit from an ESD current which enters the electronic circuit through one or more input/output pins, the protection circuit comprising: a voltage clamp circuit connectable to the or each pin, for diverting the ESD current from the or each device; and a current sensor circuit connected between the input/output pins and the voltage clamp circuit and connected to the one or more devices, the current sensor circuit for sensing the ESD current and for switching off the or each device when the sensed current exceeds a threshold value, wherein when a current flows in the current mirror circuits above a threshold value the device is caused to switch off.