TFT Array Substrate Without Protective Film
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Solution Overview
Problem
The manufacturing cost of liquid crystal display panels is high due to the complex fabrication process of thin film transistor array substrates, which involves multiple mask processes and the use of protective films that can cause defects and increase costs.
Innovation Solution
A thin film transistor array substrate is fabricated without a protective film, using a channel protective film to shield the semiconductor layer and forming a transparent conductive pattern to prevent corrosion and ensure proper signal transmission, thereby reducing the number of mask processes and eliminating the need for costly deposition equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protective film is used to protect the thin film transistor, then the transistor is protected during fabrication, but the manufacturing cost increases and defects such as pixel electrode breakage occur
Solution Approach 1:
The patent removes the protective film from the fabrication process entirely. Instead of adding a protective film and then removing it later (which causes defects and increases cost), the invention extracts this unnecessary step by using the gate insulating film itself as the protective layer during fabrication, eliminating the separate protective film layer that causes pixel electrode breakage and requires expensive deposition equipment.
Solution Approach 2:
The gate insulating film serves multiple functions: it provides electrical insulation between the gate electrode and semiconductor layer, and simultaneously acts as a protective film during subsequent fabrication steps. This multi-functionality eliminates the need for a separate protective film, reducing manufacturing complexity and cost while preventing defects.
2Manufacturing precision
If multiple mask processes are used to fabricate the thin film transistor, then the transistor structure is precisely formed, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the protective film formation step with the gate insulating film formation step. By using the gate insulating film as the protective film, the invention merges two separate processes into one, reducing the total number of mask processes from five to four, thereby simplifying the fabrication process while maintaining manufacturing precision.
Solution Approach 2:
The invention segments the fabrication process by identifying and eliminating unnecessary steps. Specifically, it segments out the separate protective film formation and removal steps, keeping only the essential transistor formation steps, which reduces process complexity while maintaining structural precision.
3Reliability
If a protective film is deposited using PECVD equipment, then the thin film transistor is protected, but the manufacturing cost increases due to equipment requirements
Solution Approach 1:
The patent extracts and eliminates the need for PECVD deposition equipment for protective film formation. By using the gate insulating film (already formed during transistor fabrication) as the protective film, the invention removes the requirement for separate protective film deposition equipment, thereby reducing capital equipment costs while maintaining transistor protection.
Data Source
AI summary
A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. A source electrode is connected to a data line crossing the gate line to define a pixel area. A drain electrode is opposed to the source electrode with a channel therebetween. A semiconductor layer is in the channel. A pixel electrode in the pixel area contacts the drain electrode over substantially the entire overlapping area between the two. A channel protective film is provided on-the semiconductor layer corresponding to the channel to protect the semiconductor layer.