Stacked CMOS Image Sensor Wafer Structure
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Solution Overview
Problem
Conventional methods for fabricating CMOS image sensors (CIS) and image signal processors (ISP) on the same substrate result in increased process complexity, cost, and degradation of ISP device characteristics due to shared lithographic processes and backside-illuminated processes that are necessary for CIS circuits.
Innovation Solution
A stacked wafer structure is proposed, where a CIS wafer and an ISP wafer are bonded using a lamination layer, with a through silicon via penetrating either the CIS or ISP wafer to electrically connect the conductive stacks, allowing for independent fabrication and reducing the need for extensive backside processing, thereby improving device characteristics and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CIS circuits and ISP circuits are formed on the same substrate, then integration is achieved, but the number of processes increases and cost increases
Solution Approach 1:
The patent divides the previously integrated CIS and ISP circuits into separate wafers. The CIS wafer contains only CIS circuits while the ISP wafer contains only ISP circuits, allowing each to be fabricated independently through their respective optimized processes without interfering with each other, thus reducing the overall number of fabrication processes required
Solution Approach 2:
The patent transitions from a planar integration approach (both circuits on the same substrate) to a three-dimensional stacked architecture where CIS and ISP wafers are vertically bonded together. This dimensional change enables independent fabrication of each wafer while achieving functional integration through the bonding interface
2Reliability
If backside-illuminated process is applied to thin substrate for CIS circuits, then CIS performance is improved, but ISP circuits on the same substrate must also undergo this process which increases fabricating time
Solution Approach 1:
By separating CIS and ISP circuits onto different wafers, the patent allows the backside-illuminated process to be applied only to the CIS wafer where it is needed for optimal CIS performance, while the ISP wafer can be processed independently without undergoing this time-consuming process, thus reducing total fabrication time
Solution Approach 2:
The patent introduces a through-silicon via structure as an intermediary electrical connection mechanism that enables signal transmission between the CIS wafer and ISP wafer after independent fabrication, eliminating the need for both wafers to undergo the same backside-illuminated processing
3Ease of manufacture
If CIS circuits and ISP circuits are fabricated by the same lithographic process, then process simplicity is maintained, but line width of ISP circuits is compromised and ISP device characteristics degrade
Solution Approach 1:
The patent segments the fabrication processes for CIS and ISP circuits into separate workflows. The ISP wafer can undergo dedicated lithographic processing optimized for precise line width control, while the CIS wafer undergoes its own optimized process sequence, eliminating the compromise that occurs when both must use the same lithographic parameters
Solution Approach 2:
The patent enables different quality standards and process parameters to be applied locally to different circuit types. The ISP circuits can be fabricated with higher precision lithographic parameters where fine line width control is critical, while CIS circuits use parameters optimized for their specific requirements, achieving local optimization rather than a uniform compromise
Data Source
AI summary
A stacked wafer structure includes a CIS wafer, an ISP wafer, a lamination layer, a through silicon via and a pixel device. The CIS wafer bonds to the ISP wafer through the lamination layer. The pixel device is disposed on the CIS wafer. The through silicon via penetrates either the CIS wafer or the ISP wafer to connect devices in CIS wafer to the devices in ISP wafer electrically.