TFT Array Panel Lithography Reduction via Unified Conductive Layer
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Solution Overview
Problem
The manufacturing of thin film transistor array panels is time-intensive and costly due to the need for repeated lithography and etching steps.
Innovation Solution
A method that reduces the number of lithography steps by forming a gate line, semiconductor layer, and data line in sequence, using photoresists with different thicknesses to selectively etch layers, and depositing a conductive film to form pixel electrodes and passivation layers, allowing for the simultaneous formation of data lines, drain electrodes, and pixel electrodes without additional lithography for the passivation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If repeated lithography and etching steps are used to form gate lines, data lines, and passivation layers, then manufacturing precision is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent combines the formation of data lines, drain electrodes, and pixel electrodes into a single lithography step by using a unified conductive layer patterned with one photoresist mask. This merging of multiple patterning operations into one step directly reduces manufacturing cycle time while maintaining the required pattern precision through careful mask design and etch process control.
Solution Approach 2:
The conductive layer serves multiple functions simultaneously - it forms data lines, drain electrodes, and pixel electrodes in a single deposition and patterning step. This multi-functionality approach eliminates the need for separate lithography steps for each conductive element, thereby reducing overall manufacturing time while preserving the precision required for each component's formation.
2Manufacturing precision
If multiple separate lithography steps are performed for different conductive layers, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the patterning of data lines, drain electrodes, and pixel electrodes into a single lithography step using one photoresist mask. This consolidation reduces process step complexity by eliminating multiple alignment and patterning operations, while the required alignment precision is maintained through the inherent registration accuracy of the single-step process and optimized etch selectivity.
3Productivity
If additional lithography step for passivation layer is omitted, then productivity is improved, but manufacturing precision may deteriorate
Solution Approach 1:
The patent merges the formation of the passivation layer with the conductive layer patterning step. The same photoresist mask used for patterning the conductive layer also defines the passivation layer regions, eliminating the need for a separate lithography step. This merging improves productivity by reducing the number of process steps, while patterning precision is maintained through the consistent mask design that simultaneously defines both conductive and passivation features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, reducing time and cost by omitting a lithography step for the passivation layer, while maintaining the structural integrity and functionality of the TFT array panel.
Implementation Method 1
depositing a conductive film on the data line and the drain electrode, forming a first photoresist on the conductive film, etching the conductive film using the first photoresist as a mask
Implementation Method 2
selectively etching the conductive layer, the semiconductor layer, and the ohmic contact layer using the second photoresist as a mask
Implementation Method 3
forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer
Data Source
AI summary
A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a data line including a source electrode and a drain electrode on the ohmic contact layer. The method further includes depositing a conductive film on the data line and the drain electrode, forming a first photoresist on the conductive film, etching the conductive film using the first photoresist as a mask to form a pixel electrode at least connected to the drain electrode, depositing a passivation layer, and removing the first photoresist to form a passivation member.