3D Optoelectronic Package Layout for Shorter Electrical Paths
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Solution Overview
Problem
Current optoelectronic packages require a large device area due to horizontal arrangement of ASIC and photonics engines, leading to decreased yield and issues with long electrical paths, which affect signal integrity and manufacturing efficiency.
Innovation Solution
The optoelectronic package design includes a carrier with a protrusion portion for power supply and a recessed cavity for optoelectronic devices, reducing the device area and using conductive elements and redistribution layers without through-silicon vias to shorten electrical paths and improve signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If optoelectronic devices and ASIC are arranged in a horizontal direction on a PCB, then electrical connection can be established, but a relatively large device area is required which decreases yield
Solution Approach 1:
The patent transitions from a horizontal 2D arrangement of optoelectronic devices and ASIC on a PCB to a vertical 3D stacked architecture. The optoelectronic devices are positioned above the ASIC on the same substrate, with electrical connections established through vertical vias and conductive structures. This dimensional change dramatically reduces the device footprint while maintaining reliable electrical connectivity between components.
2Reliability
If optoelectronic devices and ASIC are arranged horizontally on a PCB, then connection can be made, but a relatively long electrical path is created which affects signal integrity
Solution Approach 1:
The patent employs vertical stacking with direct through-substrate vias and conductive interconnects to establish electrical paths between the ASIC and optoelectronic devices. This vertical connection approach through the substrate eliminates the need for long horizontal PCB traces, significantly reducing the electrical path length and improving signal integrity by minimizing transmission distance and potential interference.
3Reliability
If through-silicon vias are used for electrical connection, then connection can be established, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent integrates the electrical connection structures directly into the substrate architecture, merging the vias and conductive paths with the substrate fabrication process. Rather than adding separate through-silicon via structures, the design incorporates conductive interconnects as part of the substrate layer stack, reducing overall device complexity while maintaining reliable electrical connections between the ASIC and optoelectronic devices.
Data Source
AI summary
An optoelectronic package and a method of manufacturing an optoelectronic package are provided. The optoelectronic package includes a carrier. The carrier includes a first region and a second region. The first region is configured to supply power to a processing unit disposed on the carrier. The second region is for accommodating at least one optoelectronic device electrically coupled to the processing unit.