3D Package Conductive Layer Alignment via Blind Hole Solder Insertion
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Solution Overview
Problem
Conventional three-dimensional packages face difficulties in alignment and stability due to hemispherical solder ends formed by capillary phenomenon, leading to increased height after joining.
Innovation Solution
A method involving forming blind holes, isolation layers, conductive layers, and solder filling, followed by reflow and cutting to expose the lower end of the conductive layer for enhanced jointing and reduced height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If solder is formed by capillary phenomenon in blind holes, then solder filling is achieved, but the solder ends form hemispherical shape causing alignment difficulty and unstable joining
Solution Approach 1:
The conductive layer is extended below the wafer surface before stacking, pre-positioning the connection interface. This preliminary action ensures that the conductive layer ends are already in optimal positions for alignment, eliminating the hemispherical solder end formation problem and enabling precise alignment during subsequent stacking operations.
Solution Approach 2:
The conductive structure is divided into two distinct parts: the conductive layer within the blind hole and the extended conductive layer below the wafer surface. This segmentation allows each part to serve a specific function - the internal conductive layer provides electrical connection while the extended portion provides a flat, accessible interface for precise alignment and stable joining with the next wafer.
2Ease of manufacture
If solder is formed by capillary phenomenon in blind holes, then solder filling is achieved, but the hemispherical shape increases the overall height of the package
Solution Approach 1:
The conductive layer is extended below the wafer surface before stacking, pre-positioning the connection interface. This preliminary action ensures that the conductive layer ends are already in optimal positions for alignment, eliminating the hemispherical solder end formation problem and enabling precise alignment during subsequent stacking operations.
Solution Approach 2:
Instead of allowing solder to form hemispherical ends that extend upward, the solution inverts the approach by extending the conductive layer downward below the wafer surface. This inversion eliminates the height-increasing hemispherical solder ends and provides a flat interface that reduces overall package height while maintaining stable joining.
3Manufacturing precision
If the lower end of conductive layer is exposed below wafer surface, then alignment and stability are improved, but additional processing steps are required
Solution Approach 1:
The extension of the conductive layer below the wafer surface is integrated with the existing blind hole formation and conductive layer deposition processes. By merging these functions into a unified manufacturing flow, the patent achieves improved alignment precision without proportionally increasing process complexity, as the conductive layer extension serves both electrical connection and alignment reference functions simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves alignment and stability by exposing the lower end of the conductive layer for better solder insertion during reflow, effectively reducing the overall height of the three-dimensional package.
Implementation Method 1
the solder enter the first hole 12 and the second hole 22 according to the capillary phenomenon so as to form the first solder 14 and the second solder 24
Data Source
AI summary
A method of making a three-dimensional package, including: (a) providing a wafer; (b) forming at least one blind hole; (c) forming an isolation layer; (d) forming a conductive layer; (e) forming a dry film; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and the isolation layer, so as to expose the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.