3D Semiconductor Package Layout Without Through-Substrate Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging System-on-Integrated-Chip (SoIC) components due to complexities in the packaging process, particularly in achieving miniaturization, higher speed, greater bandwidth, lower power consumption, and reduced latency, while also reducing process costs and eliminating the need for through-substrate vias.
Innovation Solution
A semiconductor package structure is developed that includes a first semiconductor die hybrid bonded to a plurality of second semiconductor dies, with through dielectric vias (TDVs) or through insulation vias (TIVs) formed aside the first semiconductor die for external electrical connections, eliminating the need for through-substrate vias and allowing for a TSV-free package, which reduces manufacturing costs and increases areal density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-substrate vias are used for external electrical connections, then electrical connectivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the via formation step from the substrate and relocates it to the encapsulant material. Instead of creating holes through the entire substrate, the invention forms vias only within the encapsulant after the substrate is already in place, thereby eliminating the complexity of through-substrate via fabrication while maintaining electrical connectivity functionality
Solution Approach 2:
The patent performs preliminary bonding of the substrate to the support substrate before forming the vias. This sequence allows the substrate to be securely positioned and processed first, then the vias are formed in the encapsulant material that is applied afterward, simplifying the overall manufacturing process by avoiding the need to create through-substrate holes
2Reliability
If through-substrate vias are used for external electrical connections, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the via formation operation from the substrate processing steps and relocates it to the encapsulant material processing. This eliminates the need for expensive through-substrate via fabrication equipment and processes, reducing manufacturing costs while maintaining the essential electrical connectivity function through alternative via-in-encapsulant structures
3Area of moving object
If miniaturization is pursued to increase integration density, then component size is reduced, but packaging process complexity increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking architecture. By arranging semiconductor dies in vertical layers and using through-encapsulant vias for inter-layer connections, the invention achieves high integration density in the vertical dimension while keeping individual die sizes small, thereby enabling miniaturization without proportionally increasing packaging process complexity
4Quantity of substance
If hybrid bonding is used to bond semiconductor dies, then integration density is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces an encapsulant material as an intermediary between the bonded semiconductor dies and the external environment. This encapsulant provides mechanical support and stress relief to the hybrid-bonded interfaces, compensating for minor misalignments and reducing the stringency of bonding precision requirements while maintaining high integration density through multi-die stacking
Data Source
AI summary
A package structure is provided. The package structure includes a first semiconductor package and a second semiconductor package connected to the first semiconductor package. The first semiconductor package includes an integrated circuit. The integrated circuit includes a first semiconductor die and a plurality of second semiconductor dies, the plurality of second semiconductor dies are stacked on the first semiconductor die, wherein at least one of orthogonal projections of the plurality of second semiconductor dies is partially overlapped an orthogonal projection of the first semiconductor die. The integrated circuit further includes through vias formed aside the first semiconductor and arranged in a non-overlapped region of the at least one of the orthogonal projections of the plurality of second semiconductor dies with the orthogonal projection of the first semiconductor die. A manufacturing method of a package structure is also provided.