3D Semiconductor Package Layout for Shorter High-Frequency Interconnects
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Solution Overview
Problem
Current semiconductor packaging technologies require long connection wires that induce noise and signal loss, especially at high frequencies, and are not conducive to miniaturization due to a two-dimensional layout, increasing production complexity and cost.
Innovation Solution
A semiconductor package structure with conductive structures formed on multiple surfaces, allowing connections to multiple PCBs, and using metal wires and molding compounds to encapsulate chips while exposing connections for reduced wire length and improved high-frequency performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If all connections are designed in a same plane with two-dimensional layout, then the PCB fabrication is simplified, but the connection wires become long which induces noise and signal loss
Solution Approach 1:
The patent transitions from traditional two-dimensional planar connections to three-dimensional spatial connections. Conductive structures are formed on multiple surfaces (top, bottom, and side surfaces) of the semiconductor package, enabling connections in multiple directions rather than confined to a single plane. This dimensional change shortens connection paths and reduces parasitic effects while maintaining PCB fabrication feasibility.
2Ease of manufacture
If connection wires are made long to accommodate two-dimensional layout, then the PCB fabrication is easier, but the parasitic resistance, capacitance, and inductance increase
Solution Approach 1:
By forming conductive structures on multiple surfaces including side surfaces of the semiconductor package, the patent enables three-dimensional connection routing. This reduces the length of connection wires significantly compared to two-dimensional planar routing, thereby reducing parasitic resistance, capacitance, and inductance while maintaining manufacturing feasibility.
3Device complexity
If conductive structures are formed only on one surface of the base substrate, then the packaging process is simplified, but the space utilization and connection density are limited
Solution Approach 1:
The patent forms conductive structures on multiple surfaces (top surface, bottom surface, and side surfaces) of the semiconductor package. This multi-surface approach increases connection density and space utilization without significantly complicating the packaging process, as the additional conductive structures can be formed using standard semiconductor fabrication techniques.
4Device complexity
If all connections are arranged in a single PCB plane, then the design is simpler, but the miniaturization of semiconductor devices is hindered
Solution Approach 1:
The patent enables three-dimensional connection routing by forming conductive structures on multiple surfaces including side surfaces. This allows for more compact device layouts and reduces the overall footprint required for a given number of connections, facilitating miniaturization of semiconductor devices while maintaining design manageability.
Data Source
AI summary
A semiconductor package structure includes a first substrate including first conductive pads, one or more semiconductor chips stacking on the first substrate, a second substrate on the semiconductor chips opposite to the first substrate, a molding compound on the first substrate and encapsulating the semiconductor chips and at least part of the second substrate, and a first metal wire located in the molding compound and connecting the second substrate to the semiconductor chips. The first conductive pads are on a side of the first substrate opposite to the semiconductor chips.