3D Semiconductor Pattern Yield Risk Scoring
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Solution Overview
Problem
Current 2D simulation methods fail to accurately capture risks associated with inter- or intra-layer spacing in semiconductor patterns, limiting their effectiveness in predicting yield and device performance, especially at the 22 nanometer technology node and beyond.
Innovation Solution
A 3D simulation method that generates yield scores by comparing critical dimensions between or within layers of semiconductor patterns with predefined minimum dimensions, normalizing these scores to a volume, and translating them into a risk factor, allowing for the identification and substitution of at-risk patterns with lower-risk alternatives.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If 2D simulation is used for design, then design optimization is enabled, but manufacturing risk assessment is insufficient
Solution Approach 1:
The patent transitions from 2D simulation to 3D simulation to capture vertical dimensional information including inter-layer and intra-layer spacing. This dimensional change enables accurate modeling of critical dimensions in three-dimensional semiconductor structures, providing comprehensive manufacturing risk assessment that 2D simulations cannot achieve.
2Reliability
If 3D simulation is implemented, then manufacturing risk assessment is improved, but computational complexity increases
Solution Approach 1:
The patent segments the semiconductor structure into multiple layers and extracts critical dimensions from each layer separately. By dividing the complex 3D structure into manageable components (inter-layer spacing between adjacent layers, intra-layer spacing within layers), the simulation can process each segment independently, reducing overall computational complexity while maintaining accuracy.
3Manufacturing precision
If critical dimensions are measured in 3D, then spacing risks are captured, but measurement precision requirements increase
Solution Approach 1:
The patent uses 3D simulation as an intermediary to obtain critical dimension measurements. Instead of directly measuring physical structures (which would require extremely precise physical measurement equipment), the simulation models the semiconductor patterns and extracts dimensional information computationally, achieving accurate measurement of inter-layer and intra-layer spacing without direct physical measurement.
Data Source
AI summary
Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.