Computer Aided Design TRIZ Cases
- Power State Table Merging for SoC Verification
Selective merging of power state tables reduces verification time from days to hours while maintaining comprehensive power supply relationship analysis.
- Incremental Slack Margin Propagation for Circuit Timing Optimization
Caches timing data to reuse calculations during sequential cell sizing, reducing optimization time for large circuit designs.
- Detecting High Impedance Nets via Programmable Resistors
A simulation method connects programmable resistors between transistor terminals to identify voltage fluctuations.
- Path-Based Floorplan Analysis for Timing Violations
A path-based floorplan analysis system computes timing effort metrics to predict circuit design layout difficulties.
- Automated HDL Generation for Network Packet Processors
A method generates hardware description language specifications from textual inputs defining handlers, ports, and behavioral constraints.
- Automated Power Control Circuit Generation from Behavioral Descriptions
A circuit generation system automatically synthesizes power control circuits using behavioral-level description information.
- Static Timing Analysis Checkpointing with Phase Tags
Unique phase tags enable efficient timing recalculation when boundary conditions differ, avoiding full analysis.
- At-Speed Debug Validation Architecture for FPGA Signal Monitoring
A validation system monitors internal circuit signals and routes trace data to external interfaces for real-time debugging.
- Group Bounding Box Placement for Integrated Circuit Layout Optimization
An objective function automatically sizes and positions group bounding boxes to reduce wire length and timing delay without manual iterative adjustment.