Incremental Slack Margin Propagation for Circuit Timing Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing circuit synthesis approaches face inefficiencies in timing calculations and incremental slack margin propagation, particularly for large circuit designs with many process corners and modes, leading to prolonged optimization times and poor quality results.
Innovation Solution
The proposed solution involves caching timing-related information for source drivers and sequential cells to avoid redundant calculations and incrementally propagating slack margins in a reverse-levelized processing order, allowing for efficient reuse of cached data during cell sizing and optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error based circuit optimization is performed across many process corners and modes, then timing constraints are thoroughly checked, but optimization time becomes excessively long
Solution Approach 1:
The patent performs preliminary timing analysis to identify critical paths and compute slack margins before the main optimization process. This preliminary action prepares data structures and identifies which timing constraints are most likely to be violated, allowing the optimization to focus only on relevant paths and cells rather than checking all timing constraints iteratively across all process corners.
Solution Approach 2:
The patent extracts and caches timing-related information (arrival times, slack margins, critical path data) from the full timing analysis. This extracted information is stored in data structures that can be quickly accessed during optimization without requiring full re-evaluation of all timing constraints, thereby separating the essential timing information from the complete timing analysis process.
2Measurement precision
If full timing analysis is performed for each cell size evaluation, then accurate timing information is obtained, but calculation redundancy significantly reduces efficiency
Solution Approach 1:
The patent performs preliminary timing analysis to compute arrival times and slack margins before cell sizing optimization. These preliminary results are cached and reused during the optimization process, avoiding redundant full timing analyses for each cell size evaluation while maintaining accuracy for critical paths.
Solution Approach 2:
The patent changes the state of timing information from computed-to-discarded to cached-reusable. By storing timing parameters (arrival times, slack margins) in data structures and updating them incrementally as cell sizes change, the system maintains accurate timing information without reperforming complete timing analyses, thus improving computational efficiency.
3Reliability
If incremental updates are performed throughout the entire circuit design for each cell replacement, then timing information remains accurate, but the complexity of tracking changes increases
Solution Approach 1:
The patent segments the circuit design into hierarchical levels and groups of cells. When a cell is replaced, only the relevant segments (cells at the same level and dependent cells at lower levels) are updated rather than the entire circuit design. This segmentation reduces the complexity of tracking changes while maintaining timing accuracy for affected regions.
Solution Approach 2:
The patent divides the optimization process into levels where cells are processed in groups. Timing information is updated incrementally level by level, with each level's updates building on the previous level's results. This segmented approach simplifies change tracking compared to updating the entire circuit simultaneously.
Data Source
AI summary
Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source driver can be reused when sizing a different sequential cell. The cached timing-related information for the outputs of the sequential cell can be reused when evaluating alternatives for replacing the sequential cell. Some embodiments incrementally propagate slack margins in a lazy fashion (i.e., only when it is necessary to do so for correctness or accuracy reasons) while sizing gates in the circuit design in a reverse-levelized processing order.