Power State Table Merging for SoC Verification
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Solution Overview
Problem
As System on Chip (SoC) designs become increasingly complex, traditional power verification systems face challenges in reducing verification time and memory requirements due to the explosion in size of Power State Tables (PSTs) as the number of power supplies and voltage domains grows, leading to prolonged development times before tape-out.
Innovation Solution
The Efficient Power Verification System (EPVS) addresses this by inferring relationships between power supplies, efficiently merging Power State Tables (PSTs) through a sanitization and selective merging process, retaining only relevant information, which results in a significantly smaller and quicker-to-construct merged PST, facilitating orders of magnitude speedup and resource reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional power verification systems create one large power state table containing all power supplies of the SoC, then comprehensive power verification is achieved, but verification time and memory requirements explode as Soc complexity increases
Solution Approach 1:
The patent segments the large power state table into multiple smaller power state tables, each representing a subset of power supplies. Instead of creating one comprehensive PST containing all power supplies, the system divides it into manageable segments that can be processed independently and then merged selectively, preventing the exponential growth of verification time and memory requirements.
Solution Approach 2:
The patent implements a selective merging process where only relevant power state tables are merged together based on their relationships. The merging process intelligently combines subsets of PSTs rather than all PSTs, reducing the overall size of the merged result while maintaining comprehensive verification coverage for power supply relationships.
2Reliability
If traditional power verification systems create one large power state table containing all power supplies of the SoC, then comprehensive power verification is achieved, but memory requirements explode as Soc complexity increases
Solution Approach 1:
The patent segments the large power state table into multiple smaller power state tables, each representing a subset of power supplies. This segmentation reduces the memory footprint by avoiding the creation of one massive PST that would require exponential memory resources, instead using multiple smaller tables that fit within available memory constraints.
Solution Approach 2:
The patent implements a selective merging process where only relevant power state tables are merged together based on their relationships. The merging process intelligently combines subsets of PSTs rather than all PSTs, reducing the overall size of the merged result while maintaining comprehensive verification coverage, thereby reducing memory requirements.
3Use of energy by moving object
If the number of power supplies and voltage domains increases to handle complex Soc designs, then power consumption management improves, but the size of power state tables explodes
Solution Approach 1:
The patent segments the power state table based on power supply relationships and voltage domains. By dividing the PST into smaller segments that represent subsets of power supplies, the system can manage complex SoC designs with multiple voltage domains without creating an exponentially large single table, thus reducing device complexity while maintaining detailed power management capabilities.
Solution Approach 2:
The patent implements selective merging of power state tables based on power supply relationships. By merging only relevant subsets of PSTs rather than all tables, the system handles complex power consumption management scenarios while keeping the merged result size manageable, avoiding the explosion of device complexity.
4Measurement precision
If traditional power verification systems process all power state tables, then complete power supply relationship analysis is achieved, but verification time increases from hours to days
Solution Approach 1:
The patent segments the power verification process into smaller tasks based on power supply relationships. Instead of processing all power state tables in one comprehensive analysis, the system divides the verification into segments that can be processed in parallel or sequentially in a more efficient manner, improving verification throughput while maintaining analysis precision.
Solution Approach 2:
The patent implements selective merging of power state tables based on relevant power supply relationships. By merging only the necessary subsets of PSTs rather than all tables, the system reduces the computational workload while maintaining complete power supply relationship analysis, thereby improving verification productivity from hours to days without sacrificing measurement precision.
Data Source
AI summary
A power verification system requires a combination of design and its power intent. A power intent (PI) input specifies the power architecture of a design through specification of power/voltage domains, their corresponding power supplies and a collection of power management devices. Power state tables (PSTs) specified in PI capture the legal combinations of power states (voltage values) for the various sets of supply nets or supply ports of a design. A power verification system requires determining the power supply relationships of voltage/power domains which requires merging of PSTs. The system described efficiently merges PSTs by iteratively selecting only a subset of PSTs that are relevant to the supply pair of interest, that are pruned initially and as the merge progresses. This provides orders of magnitude speedup and resource reduction. A user interface allows display of identified power verification failures and may include an input device for facilitating correction of at least one of the electronic circuit design and the power intent file.