Path-Based Floorplan Analysis for Timing Violations
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Solution Overview
Problem
Conventional floorplanning tools in electronic design automation (EDA) take a long time to complete and often produce poor quality results due to the increasing size and complexity of integrated circuit (IC) designs, and they fail to provide adequate insight into the impact of a given floorplan on the final optimized circuit, leading to potential mistakes and unidentified problems.
Innovation Solution
The method computes a timing effort metric by calculating the physical distance and timing distance between circuit objects, using intrinsic delays and a scaling factor, to predict and visualize the difficulty of meeting timing constraints, allowing for the identification of sub-optimal floorplans and the rearrangement of circuit design layout to improve timing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional floorplanning tools are used to arrange circuit blocks, then the design process can be completed, but the design time becomes very long and the quality of results deteriorates
Solution Approach 1:
The patent computes timing effort metrics during the floorplanning stage itself, before the full design flow is executed. This preliminary analysis identifies potential timing violations and difficult-to-fix paths early, allowing designers to adjust the floorplan proactively rather than discovering problems later in the design process, thereby reducing overall design time while improving floorplan quality
Solution Approach 2:
The patent introduces a feedback mechanism that provides timing effort metrics and difficulty assessments back to the floorplanning stage. By computing metrics such as physical distance, timing distance, and timing effort for each timing path, the system gives designers actionable feedback about which paths are most problematic, enabling targeted improvements to floorplan quality without requiring exhaustive full-design-flow executions
2Loss of information
If conventional floorplanning tools are used, then circuit blocks can be arranged, but adequate insight into the impact of floorplan on final optimized circuit is not provided
Solution Approach 1:
The patent introduces timing effort metrics as an intermediary between the floorplan layout and the final optimized circuit performance. These metrics (physical distance, timing distance, timing effort) serve as intermediate representations that provide insight into how the floorplan will impact timing without requiring full optimization to be completed, thereby reducing information loss while avoiding the complexity of running complete design flows for analysis
3Loss of time
If timing analysis is performed without computing timing effort metric, then the process is simpler, but timing violations cannot be identified before full design flow
Solution Approach 1:
The patent performs preliminary timing analysis by computing timing effort metrics during floorplanning, before the full design flow is executed. This early computation of physical distance, timing distance, and timing effort identifies potential timing violations and difficult-to-fix paths in advance, allowing designers to address issues proactively and reducing the time needed to identify and resolve timing problems later in the design process
Data Source
AI summary
Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.