3D PCB Assembly Vertical Stacking for Signal Integrity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current printed circuit board (PCB) assemblies face challenges with increasing component density, leading to space constraints, longer and more complex signal lines, which result in signal integrity issues due to electrical disturbances and electromagnetic interference.

Innovation Solution

The implementation of a 3D electronic system assembly with secondary circuit substrates mounted over a main circuit substrate, using conductive interconnect structures to mechanically and electrically couple them, allowing for higher component density, shorter signal paths, and improved thermal performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If component density on PCB is increased to meet space constraints, then more components can be integrated, but signal lines become longer and more complex leading to signal integrity issues

Engineering Contradiction:
Improvecomponent densityVSAvoidsignal integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from a traditional 2D PCB layout to a 3D stacked architecture where circuit substrates are arranged vertically. This dimensional change allows components to be placed in multiple layers, reducing the horizontal distance between them and shortening signal paths while maintaining high component density. The vertical stacking enables direct electrical connections between layers through conductive interconnect structures, improving signal integrity despite increased component integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If more components are placed on PCB to increase functionality, then system capabilities improve, but space constraints and signal line complexity increase

Engineering Contradiction:
Improvesystem functionalityVSAvoidPCB area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The invention utilizes vertical stacking to arrange multiple circuit substrates in the third dimension, enabling high component integration without increasing the horizontal PCB footprint. Each substrate layer can host additional components and circuitry, effectively multiplying the functional capacity within the same planar area. This 3D configuration allows the system to achieve enhanced adaptability and versatility while maintaining compact form factor.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If traditional 2D PCB layout is used, then manufacturing is simpler, but thermal performance and signal integrity deteriorate

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidthermal performance
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent employs vertical stacking of circuit substrates with conductive interconnect structures that provide both electrical connectivity and thermal conduction pathways. The multiple layers and interconnect structures create extended thermal management surfaces and heat dissipation routes, improving thermal performance compared to traditional 2D layouts. The 3D architecture allows heat to be distributed across multiple substrates and dissipated more efficiently through the vertical structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240206069A1Printed circuit board over printed circuit board assembly
Publication Date: 2024.06.20 MICRON TECHNOLOGY INC
  • US20240206069A1 patent drawing
  • US20240206069A1 patent drawing
  • US20240206069A1 patent drawing

AI summary

An electronic system assembly includes a first circuit substrate having a surface, wherein the surface has a two-dimensional area defined in a first dimension and a second dimension; a plurality of first semiconductor chip packages mounted on and electrically coupled to the surface; a plurality of second circuit substrates positioned over the surface, wherein each first semiconductor chip package is arranged between the surface and a respective second circuit substrate in a third dimension; a plurality of conductive interconnect structures that extend in the third dimension, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups, and wherein each interconnect group connects a different second circuit substrate to the first circuit substrate; and a plurality of second semiconductor chip packages, wherein each second semiconductor chip package is mounted and electrically coupled to a respective second circuit substrate.