3D Phase-Change Memory Array for Low-Power In-Memory MAC
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Solution Overview
Problem
Existing technologies face challenges in efficiently performing multiplication and accumulation operations in memory systems, particularly in terms of energy efficiency and power consumption, especially in applications like training artificial neural networks.
Innovation Solution
A three-dimensional memory cell array using phase-change material memory cells connected to transistors is implemented, allowing for in-memory computations of multiplication and accumulation, with reduced operating voltages and improved power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple sets of logic circuits are configured in arrays to perform multiplications and accumulations in parallel, then computation speed is improved, but energy consumption increases
Solution Approach 1:
The patent merges computation and storage functions into a single integrated memory array structure. Weight values are stored directly in the memory array, and input signals are applied through word lines to simultaneously access multiple memory cells for parallel multiplication operations, eliminating the need for separate logic circuits and reducing overall energy consumption while maintaining high computation speed
Solution Approach 2:
The memory array serves multiple functions: it stores weight values, performs multiplication operations through current modulation, and accumulates results through parallel current summation. This multi-functional design eliminates the need for dedicated computation hardware, reducing energy consumption while maintaining computational efficiency
2Use of energy by moving object
If phase-change material memory cells are used with transistors for in-memory computation, then energy efficiency is improved, but device complexity increases
Solution Approach 1:
The patent replaces traditional digital logic circuits with a physical memory array based on phase-change material that performs computation through electrical current modulation. The resistance states of phase-change material cells modulate currents according to weight values, enabling analog multiplication without complex digital logic, thus reducing device complexity while improving energy efficiency
Solution Approach 2:
The patent utilizes the resistance parameter changes of phase-change material to represent different weight values. By controlling the resistance state of each memory cell, the system achieves programmable weight values that can be read out as current modulations, enabling flexible computation without requiring complex reconfigurable logic circuits
3Quantity of substance
If a three-dimensional memory cell array is implemented for high-density storage, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional memory array architecture by stacking multiple layers of memory cells vertically. This dimensional change dramatically increases storage capacity without proportionally increasing the planar footprint, and the vertical stacking approach allows for standardized manufacturing processes that reduce precision requirements compared to achieving high density through planar scaling alone
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a high-density, energy-efficient memory cell array that significantly reduces power consumption during frequent data modifications, enhancing the efficiency of operations like training neural network weights.
Implementation Method 1
The memory cells can be implemented via phase-change material
Implementation Method 2
perform multiplication and accumulation operations in the electrical domain
Data Source
AI summary
A memory device having: a first local digit line configured to extend in a first direction; a second local digit line configured in parallel with the first local digit line; a plurality of unit cells stacked in the first direction and sandwiched between the first local digit line and the second local digit line, each respective unit cell among the plurality of unit cells configured to connect the first local digit line to the second local digit line in a second direction that is perpendicular to the first direction, the respective unit cell having a transistor and a memory cell; and a plurality of wordlines configured to extend in a third direction that is perpendicular to the first direction and the second direction, where transistors in the plurality of unit cells are connected to the wordlines.