3D Pixel Capacitor Isolation in CMOS Image Sensors
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Solution Overview
Problem
Existing CMOS image sensors face challenges in applying capacitors with three-dimensional shapes due to electrical connections between adjacent pixels, hindering improved image quality.
Innovation Solution
A solid-state imaging element with capacitors formed in a three-dimensional shape between upper and lower wirings, isolated by an isolation unit to prevent electrical connections between adjacent capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If capacitors with three-dimensional shapes are applied to CMOS image sensors to improve image quality, then image quality and dynamic range are improved, but electrical connections between adjacent capacitors cannot be prevented
Solution Approach 1:
The patent introduces isolation units that divide and separate adjacent capacitors, creating independent electrical zones. This segmentation prevents unwanted electrical connections between capacitors of neighboring pixels while maintaining the three-dimensional structure, thus resolving the contradiction between improved image quality and electrical isolation reliability.
Solution Approach 2:
The isolation units act as intermediary elements positioned between adjacent capacitors. These units serve as electrical barriers that prevent direct connection between capacitors while allowing each capacitor to maintain its three-dimensional shape and capacitance function, thereby enabling both high image quality and proper electrical isolation.
2Quantity of substance
If three-dimensional capacitors are used to increase capacitance, then dynamic range is expanded, but electrical isolation between adjacent pixels becomes difficult to achieve
Solution Approach 1:
The isolation units segment the pixel array into independent electrical zones, allowing each pixel to maintain high capacitance through three-dimensional capacitors without electrical interference from neighbors. This segmentation approach enables increased capacitance while managing the complexity through systematic isolation structures.
Solution Approach 2:
The patent employs isolation units that extend in the vertical dimension (between upper and lower wirings) to achieve electrical isolation. By utilizing the third dimension for isolation rather than only planar separation, the design maintains high capacitance in the pixel area while achieving isolation through vertical positioning of the isolation units.
Data Source
AI summary
The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic device that can achieve higher image quality. The solid-state imaging element includes a plurality of pixels, a capacitor provided for each of the pixels and formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixels, and an isolation unit that electrically isolates capacitors of adjacent pixels from each other. Then, the isolation unit is provided for each of the pixels so as to surround the capacitor, and an interlayer insulating film is provided between the isolation units of the respective pixels. The present technology can be applied to a CMOS image sensor, for example.