3D Planar Capacitor Structure for Semiconductor Integration Density
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Solution Overview
Problem
The integration degree of capacitors in semiconductor devices is low, limiting the size reduction of semiconductor devices due to the large occupied area of capacitors in existing technologies.
Innovation Solution
A semiconductor device with a substrate having a first trench and a first insulating layer formed on the surface and inside the trench, with a conducting layer on the insulating layer, forming a three-dimensional planar structure that reduces the occupied area of capacitors without changing the effective area, thereby improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional planar capacitor structure is used, then manufacturing process is simple, but integration degree is low and device size is large
Solution Approach 1:
The patent transforms the traditional two-dimensional planar capacitor structure into a three-dimensional structure by forming trenches in the substrate and filling them with insulating and conducting layers. This vertical stacking approach reduces the horizontal occupied area while maintaining manufacturing feasibility through sequential layer deposition processes.
Solution Approach 2:
The patent implements nesting by placing the conducting layer inside the trench formed in the substrate, with the insulating layer surrounding the conducting layer. This nested configuration (substrate trench containing insulating layer containing conducting layer) maximizes space utilization and reduces the overall device footprint.
2Area of stationary object
If capacitor integration degree is increased, then device size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the capacitor structure into distinct functional layers: substrate, trench, insulating layer, and conducting layer. This segmentation allows each component to be manufactured and optimized independently, simplifying the overall manufacturing process despite the three-dimensional configuration.
Solution Approach 2:
The trench structure serves multiple functions: it provides mechanical support, defines the capacitor geometry, and enables the vertical stacking arrangement. This multi-functionality reduces the need for additional structural elements, thereby controlling manufacturing complexity while achieving high integration.
Data Source
AI summary
This disclosure provides a semiconductor device, a method of manufacturing the same, a 3D NAND memory, and a memory system. The semiconductor device includes a substrate having a first trench at a surface thereof, and a first insulating layer formed on the surface of the substrate and inside the first trench. The first insulating layer formed inside the first trench forms a second trench that is embedded in the first trench. The semiconductor device further includes a conducting layer formed on a surface of the first insulating layer away from the substrate and inside the second trench.