3D Semiconductor Power Delivery Path for Dense Stacked Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in 3D stacked chip integration due to the degradation of wiring performance and limited connectivity between layers, primarily because of the mismatch in processing temperatures required for transistor and wiring layers, leading to misalignment and defects in vertical contact dimensions.
Innovation Solution
The development of a 3D semiconductor device architecture that includes single crystal transistors and isolation layers, with a power delivery path and capacitors for decoupling noise, and a thermal conductive path, using optical annealing to repair defects and activate dopants without damaging underlying metal interconnects, and employing a shield/heat sink layer to manage heat and prevent damage to metal layers during high-temperature processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are constructed in 3 dimensions along with wires, then transistor density and performance are improved, but the wiring layers are damaged due to high temperature processing
Solution Approach 1:
The patent divides the semiconductor structure into separate levels: a first level containing transistors and a second level containing wiring layers. This segmentation allows independent processing of each level, enabling the transistor level to be processed at high temperatures without damaging the wiring level, thus resolving the contradiction between achieving high transistor density through 3D stacking and maintaining wiring layer integrity
Solution Approach 2:
The patent transitions from 2D planar integration to 3D vertical stacking by placing transistor levels and wiring levels at different vertical positions. The wiring layers are positioned above the transistor levels, creating a three-dimensional architecture that allows high-temperature transistor processing without compromising the underlying or adjacent wiring structures
2Reliability
If alternative 3D stacking architectures are used with separate wafers, then high temperature damage is avoided, but connectivity between layers is limited due to large contact sizes and misalignment
Solution Approach 1:
The patent merges the transistor level and wiring level into a single integrated semiconductor structure rather than using separate bonded wafers. This unified structure eliminates alignment issues between separate layers and enables precise formation of contacts and via holes through standard semiconductor processing techniques, achieving both wiring protection and high connectivity density
Solution Approach 2:
The patent introduces intermediate structures such as isolation layers and specific contact formation techniques that mediate between the transistor level and wiring level. These intermediary elements enable precise electrical connections while maintaining the structural integrity and thermal protection of the wiring layers
3Productivity
If standard transistors are fabricated in a pattern allowing high density connectivity, then connectivity density is improved, but heat removal becomes inefficient
Solution Approach 1:
The patent applies different structural characteristics to different regions of the semiconductor device. The transistor regions are optimized for high-density connectivity with closely spaced transistors and efficient interconnect structures, while the wiring layers are positioned and designed to facilitate heat dissipation pathways. This local differentiation allows simultaneous achievement of high connectivity density and effective thermal management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density connectivity between layers, maintains transistor and wiring reliability, and improves heat management, overcoming the limitations of existing 3D stacking technologies by allowing for high-performance transistors and efficient power distribution while preventing damage to metal interconnects.
Implementation Method 1
incorporating a heat spreader or heat sink layer to manage heat distribution and protect sensitive metal interconnects during defect annealing
Implementation Method 2
utilizing a power delivery path connected to transistors
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the plurality of capacitors include functioning as a decoupling capacitor to mitigate power supply noise.