3D RC Circuit Layout in Semiconductor Memory for Area Reduction
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Solution Overview
Problem
Existing semiconductor storage devices have a large size due to the size of the RC circuit, which occupies a significant area and hinders further miniaturization.
Innovation Solution
The semiconductor storage device incorporates an RC circuit with a resistive portion and a capacitive portion connected in series, where the resistive portion is designed to occupy a smaller area by arranging the conductors and contacts in a specific configuration within the area where the capacitive portion is formed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the RC circuit is arranged in a conventional layout, then the electrical functionality is maintained, but the device area is excessively large
Solution Approach 1:
The patent transitions the RC circuit layout from a planar two-dimensional arrangement to a three-dimensional stacked configuration. The capacitor is positioned vertically above the resistor with direct vertical connections, utilizing the third dimension (height) to reduce the footprint area while maintaining electrical functionality.
Solution Approach 2:
The RC circuit components are nested vertically within each other's spatial envelope. The capacitor structure is positioned directly over the resistor structure, with connection conductors extending vertically through intermediate layers, creating a compact nested arrangement that minimizes overall device area.
2Area of stationary object
If the RC circuit size is reduced, then the device miniaturization is enabled, but the manufacturing precision requirements increase
Solution Approach 1:
The RC circuit is segmented into distinct vertical layers: the resistor layer at the bottom, intermediate connection layers, and the capacitor layer at the top. Each layer can be fabricated and aligned independently, with the segmentation allowing for modular manufacturing processes that reduce overall alignment complexity despite the compact size.
Solution Approach 2:
The patent employs symmetric and regular geometric patterns in the conductor traces and component layouts, creating equipotential-like alignment references that simplify the manufacturing process. The regular spacing and symmetrical arrangement of connection points provide natural alignment cues that reduce precision requirements.
Data Source
AI summary
A semiconductor storage device includes a memory cell array and a peripheral circuit disposed at least partially below the memory cell array. The peripheral circuit includes an RC circuit in which a resistive portion and a capacitive portion are electrically connected to each other in series. The resistive portion includes first and second lower conductors at a level that is below the memory cell array, an upper conductor at a level that is above the memory cell array, a first contact that connects the first lower conductor to the upper conductor, and a second contact that connects the upper conductor to the second lower conductor. The first lower conductor, the first contact, the upper conductor, the second contact, and the second lower conductor are electrically connected in series in this order and the first lower conductor is closest to the capacitive portion.