3D ReRAM Cell Stacking for Lower Forming Voltage
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Solution Overview
Problem
Conventional ReRAM devices require high forming voltages as the switching area scales down, leading to increased power consumption and reduced device density due to the need for external high-voltage devices and area penalties when attempting to reduce forming voltage.
Innovation Solution
The implementation of a three-dimensional ReRAM structure with vertically stacked cells and a stepped configuration, achieved through isotropic etching of dielectric layers, allows for a larger memory cell area without increasing the overall device footprint, thereby reducing the forming voltage and enhancing device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the switching area of the ReRAM device is scaled down, then the device density is improved, but the forming voltage increases leading to increased power consumption
Solution Approach 1:
The patent transitions from a conventional two-dimensional ReRAM structure to a three-dimensional vertically stacked structure. Multiple ReRAM cells are stacked along the vertical direction, allowing multiple memory cells to occupy the same footprint area. This dimensional change enables higher device density without reducing the switching area of individual cells, thereby maintaining low forming voltages while achieving improved density.
2Power
If the switching area of the ReRAM device is increased to reduce the forming voltage, then the forming voltage is reduced, but the device footprint increases reducing the special density
Solution Approach 1:
The patent utilizes vertical stacking to accommodate multiple ReRAM cells with larger switching areas without increasing the lateral footprint. By stacking cells in the vertical dimension, the device achieves both low forming voltages (requiring larger cell areas) and high density (maintaining small footprint), effectively resolving the contradiction between power consumption and area utilization.
3Ease of manufacture
If conventional ReRAM structure is used, then the fabrication process is simple, but the forming voltage is high requiring external devices
Solution Approach 1:
The vertically stacked ReRAM structure enables multiple cells to be integrated within a compact footprint while maintaining compatibility with existing fabrication processes. The three-dimensional configuration allows for reduced forming voltages without requiring complex external voltage provision systems, as each cell can be independently formed at lower voltages due to the optimized vertical architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a lower forming voltage for ReRAM cells while maintaining device density, eliminating the need for external high-voltage devices and avoiding area penalties, thus improving the scalability and efficiency of ReRAM devices.
Implementation Method 1
performing an isotropic etching process on the dielectric layers so that the dielectric layers are recessed in a lateral direction relative to the first electrodes
Implementation Method 2
Oxygen vacancies in a metal oxide layer of a ReRAM device are the building blocks of a current conducting filament
Data Source
AI summary
A resistive random access memory (ReRAM) device and a method for forming the device are provided. The ReRAM device includes a first electrode, a resistive switching element layer in contact with the first electrode, and a plurality of second electrodes in contact with the resistive switching element layer. Protruding portions of the first electrode and the resistive switching element layer overlap with the plurality of second electrodes in a vertical direction of the ReRAM device to form a plurality of vertically stacked ReRAM cells.